From patchwork Fri Apr 9 11:13:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 418999 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8E8DC433B4 for ; Fri, 9 Apr 2021 11:17:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7CD696100A for ; Fri, 9 Apr 2021 11:17:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234108AbhDILR5 (ORCPT ); Fri, 9 Apr 2021 07:17:57 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:49727 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233968AbhDILRu (ORCPT ); Fri, 9 Apr 2021 07:17:50 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617967057; x=1649503057; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7KxROLHftHxojszu7kto2DqA+KMwMJOPHCNZ1DYkUlo=; b=gcQLhNr+HgOv83+1iBIuGxt/L3KPjhkjJBUuH31dyzcIrKRNS/mfuYLt Nb+7ybnoM9S0R40jpbeImvpLP4t0ZJSDomscJiO94iiiMvf5+OJsQFkkn k/4Gs8wS5TR8P3weulWn7KH1CetobDlk1KCvSJd5Smzuze1Bs40c1aJEr S6rgmvIgKu2MwF6j/BAc/5A+tfx3ARfbwkglz/i8S/55/B506qeoyDkEc xnv3ljpHIpKmJZ9wQGrkULz4LwZwT9IhESF7esb/BXHmv3o58MD6j5fvB 452N4Tj/ZKW3C8cpoJi6g2gLS4qtTaDpSMFLClcGO3DvTZb8XaPWIWepb Q==; IronPort-SDR: KX6jBs2HFEbi9n0Lx5fU5m1iiLDapwzcupqUGRo8LBt4GwWAGjlfgKtIf7FbisDxH8MAHSwMUw P6sHg2uWJMXA9lEEkCVovjkfOUr752vAL3WbaVSexUWoNnnN6NrmKIKCB/sn9CgXh1f1mCJHE0 LosfCkFb/DHEc9YXndoLI+bWV/XE3/QjkVcb2Wnhgmi9r5j4hmUvWfGSPIzx4EhBtqrMjqUnfL X2ZHiAj/3RIhWnkpHTKJYAO7xUXvZFjRSQ/Ti1Sjx4UXj8cUgCBc0kbC0pe6gBa6OyxeV2LxKx TJ8= X-IronPort-AV: E=Sophos;i="5.82,209,1613458800"; d="scan'208";a="113022631" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 Apr 2021 04:17:37 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Fri, 9 Apr 2021 04:17:36 -0700 Received: from m18063-ThinkPad-T460p.mchp-main.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Fri, 9 Apr 2021 04:17:23 -0700 From: Claudiu Beznea To: , , , , CC: , , , Claudiu Beznea Subject: [PATCH v2 17/24] ARM: at91: pm: add sama7g5 ddr controller Date: Fri, 9 Apr 2021 14:13:38 +0300 Message-ID: <20210409111345.294472-18-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210409111345.294472-1-claudiu.beznea@microchip.com> References: <20210409111345.294472-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add SAMA7G5 DDR controller to the list of DDR controller compatibles. At the moment there is no standby support. Adapt the code for this. Signed-off-by: Claudiu Beznea --- arch/arm/mach-at91/pm.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 65e13769cf50..5dc942a2012d 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -548,6 +548,7 @@ static const struct of_device_id ramc_ids[] __initconst = { { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] }, { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] }, { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] }, + { .compatible = "microchip,sama7g5-uddrc", }, { /*sentinel*/ } }; @@ -565,9 +566,11 @@ static __init void at91_dt_ramc(void) panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx); ramc = of_id->data; - if (!standby) - standby = ramc->idle; - soc_pm.data.memctrl = ramc->memctrl; + if (ramc) { + if (!standby) + standby = ramc->idle; + soc_pm.data.memctrl = ramc->memctrl; + } idx++; }