From patchwork Mon Apr 5 20:08:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien Parent X-Patchwork-Id: 415409 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D5B7C43460 for ; Mon, 5 Apr 2021 20:08:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 08517613D1 for ; Mon, 5 Apr 2021 20:08:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240564AbhDEUIk (ORCPT ); Mon, 5 Apr 2021 16:08:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57984 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240546AbhDEUIj (ORCPT ); Mon, 5 Apr 2021 16:08:39 -0400 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D5BAC061788 for ; Mon, 5 Apr 2021 13:08:32 -0700 (PDT) Received: by mail-wm1-x32f.google.com with SMTP id z6-20020a1c4c060000b029010f13694ba2so6137810wmf.5 for ; Mon, 05 Apr 2021 13:08:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zBI59S0esvtyRJVOZTHC86ExpUhwst9TBLwdi/kDYn8=; b=tiGffN4digjOme3ZvvrFri/s9NDzwTOWr1qHeG7BhTyV469zeXcoPoWnAOWuxGsYAi Az5xcWk7WCcViBojAQEXw5P/uuykrC+FsLOcTwv9ubhKl9S3/hJRgTCCENfz+BrqWfC8 ba6I1hvGtwuyC8L6h+lyGyzCHxZ/QLnrrzO4Zglshtj0IhwYd2Kxug+1/FTNIYOfL3VW SBUcPjQIKzojr6sSAiwT8Li40JANAE3kv9jDylR8RBujP55GTbjMeQ6Y78a9pvYvtWZN cacolBfsSb0/bf5zJ145x7bvf2NLcro51gQMdpFj38C9jhg4E3+wNxMbsAD0xenGezdf be3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zBI59S0esvtyRJVOZTHC86ExpUhwst9TBLwdi/kDYn8=; b=ffaIjJexPxlePyNFBBsEQS8pGzp2qTWZswytMhzpYS0/REw2HREm5QtvNSn7PvWIA/ 1keAht81bEEkDB2cz/BufKnHwpNzuikzhjkLH5NPP5VSz2kQ47rpflfUOSA0q4GEyFow r0ZFrrDX2C17n2xQTBHMQOULr1k0IdhwIq6O3lJXsfuAt2P6fSGRKQ2FYk4M0/WLsJ6d 6aZNZSSmIr8xOwM/EtDuRE6NaaHQ2xxaW0fCOIHbNOx7uoPdl9WR+r0yrBVJrHx+9zD0 Q685r4CeFHLFtUzMSK/go5NHct5e0eqkXAssB+KORtRQWUNkcUNBY5APbSeoem9pCKMx trIg== X-Gm-Message-State: AOAM532QEQlLY/PKFrf5TiAjh5Dv3IPazNBhJG7qe3IaJ8el6txyckR3 ToHO8VKuJTryDm+tVtPejpugPA== X-Google-Smtp-Source: ABdhPJyfy0YtdT4isJjzVUiZ5iElNhki0/lybno+DvYH9leDZPbn06qlgznbrXa6NBC610NsrAp3HA== X-Received: by 2002:a05:600c:228d:: with SMTP id 13mr689696wmf.49.1617653310820; Mon, 05 Apr 2021 13:08:30 -0700 (PDT) Received: from localhost.localdomain ([88.160.162.107]) by smtp.gmail.com with ESMTPSA id v185sm609420wmb.25.2021.04.05.13.08.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Apr 2021 13:08:30 -0700 (PDT) From: Fabien Parent To: Rob Herring , Matthias Brugger Cc: mkorpershoek@baylibre.com, Fabien Parent , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/5] arm64: dts: mediatek: mt8167: add some DRM nodes Date: Mon, 5 Apr 2021 22:08:21 +0200 Message-Id: <20210405200821.2203458-5-fparent@baylibre.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20210405200821.2203458-1-fparent@baylibre.com> References: <20210405200821.2203458-1-fparent@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add all the DRM nodes required to get DSI to work on MT8167 SoC. Signed-off-by: Fabien Parent --- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 149 +++++++++++++++++++++++ 1 file changed, 149 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi index 3ba03ca749b2..8ca92d6b203a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -16,6 +16,19 @@ / { compatible = "mediatek,mt8167"; + aliases { + aal0 = &aal; + ccorr0 = &ccorr; + color0 = &color; + dither0 = &dither; + dsi0 = &dsi; + ovl0 = &ovl0; + pwm0 = &disp_pwm; + rdma0 = &rdma0; + rdma1 = &rdma1; + wdma0 = &wdma; + }; + soc { topckgen: topckgen@10000000 { compatible = "mediatek,mt8167-topckgen", "syscon"; @@ -114,6 +127,13 @@ vdecsys: syscon@16000000 { #clock-cells = <1>; }; + mutex: mutex@14015000 { + compatible = "mediatek,mt8167-disp-mutex"; + reg = <0 0x14015000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + }; + pio: pinctrl@1000b000 { compatible = "mediatek,mt8167-pinctrl"; reg = <0 0x1000b000 0 0x1000>; @@ -126,6 +146,135 @@ pio: pinctrl@1000b000 { interrupts = ; }; + rdma1: rdma1@1400a000 { + compatible = "mediatek,mt8167-disp-rdma", + "mediatek,mt2701-disp-rdma"; + reg = <0 0x1400a000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + iommus = <&iommu M4U_PORT_DISP_RDMA1>; + mediatek,larb = <&larb0>; + }; + + disp_pwm: disp_pwm@1100f000 { + compatible = "mediatek,mt8167-disp-pwm", + "mediatek,mt8173-disp-pwn"; + reg = <0 0x1100f000 0 0x1000>; + #pwm-cells = <2>; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + clocks = <&topckgen CLK_TOP_PWM_SEL>, + <&topckgen CLK_TOP_PWM_MM>, + <&mmsys CLK_MM_DISP_PWM_26M>, + <&mmsys CLK_MM_DISP_PWM_MM>; + clock-names = "pwm_sel", + "pwm_mm", + "main", + "mm"; + status = "disabled"; + }; + + dsi: dsi@14012000 { + compatible = "mediatek,mt8167-dsi", + "mediatek,mt2701-dsi"; + reg = <0 0x14012000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DSI_ENGINE>, + <&mmsys CLK_MM_DSI_DIGITAL>, + <&mipi_tx>; + clock-names = "engine", "digital", "hs"; + phys = <&mipi_tx>; + phy-names = "dphy"; + status = "disabled"; + }; + + mipi_tx: mipi_dphy@14018000 { + compatible = "mediatek,mt8167-mipi-tx", + "mediatek,mt2701-mipi-tx"; + reg = <0 0x14018000 0 0x90>; + clocks = <&topckgen CLK_TOP_MIPI_26M_DBG>; + clock-output-names = "mipi_tx0_pll"; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; + + ovl0: ovl0@14007000 { + compatible = "mediatek,mt8167-disp-ovl", + "mediatek,mt8173-disp-ovl"; + reg = <0 0x14007000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_OVL0>; + iommus = <&iommu M4U_PORT_DISP_OVL0>; + mediatek,larb = <&larb0>; + }; + + rdma0: rdma0@14009000 { + compatible = "mediatek,mt8167-disp-rdma", + "mediatek,mt2701-disp-rdma"; + reg = <0 0x14009000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_RDMA0>; + iommus = <&iommu M4U_PORT_DISP_RDMA0>; + mediatek,larb = <&larb0>; + }; + + color: color@1400c000 { + compatible = "mediatek,mt8167-disp-color", + "mediatek,mt8173-disp-color"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_COLOR>; + }; + + ccorr: ccorr@1400d000 { + compatible = "mediatek,mt8167-disp-ccorr", + "mediatek,mt8183-disp-ccorr"; + reg = <0 0x1400d000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_CCORR>; + }; + + aal: aal@1400e000 { + compatible = "mediatek,mt8167-disp-aal"; + reg = <0 0x1400e000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_AAL>; + }; + + gamma: gamma@1400f000 { + compatible = "mediatek,mt8167-disp-gamma", + "mediatek,mt8173-disp-gamma"; + reg = <0 0x1400f000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_GAMMA>; + }; + + dither: dither@14010000 { + compatible = "mediatek,mt8167-disp-dither"; + reg = <0 0x14010000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_DITHER>; + }; + + wdma: wdma0@1400b000 { + compatible = "mediatek,mt8167-disp-wdma"; + reg = <0 0x1400b000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_WDMA>; + iommus = <&iommu M4U_PORT_DISP_WDMA0>; + mediatek,larb = <&larb0>; + }; + mmsys: mmsys@14000000 { compatible = "mediatek,mt8167-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>;