From patchwork Wed Mar 31 10:59:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 413036 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2FD42C433EB for ; Wed, 31 Mar 2021 11:00:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CBC4C61957 for ; Wed, 31 Mar 2021 11:00:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235113AbhCaLAM (ORCPT ); Wed, 31 Mar 2021 07:00:12 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:43949 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235338AbhCaK75 (ORCPT ); Wed, 31 Mar 2021 06:59:57 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617188396; x=1648724396; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7KxROLHftHxojszu7kto2DqA+KMwMJOPHCNZ1DYkUlo=; b=vWfcUAdz2BXqCgSnm7TO4KMlBiCAXB3URyFXkdALZVIeX0JEPJhtEWVa ivRX8VC/tn2/KWQXvmC5c6ABnSo07Z4cMMq+4CNs5SaEnA/3OfBL9i8Io oXRmKc98bJ0qE3aZjKm136K83D19odx1o+Hb4bXpR1y5iOrOxckFZPyTo t+HXw3PTNbl3Q47qYpHRSaLgPXMizN89Kai7UG7pLB90jzSb7PX8vztxn 4/uKGosTu3XVCkOG8q3quunY99t9waa8POMqFFo8czbWg2MtHNWzMyY7R 922RYrjNzyAM70iaSdzV8elUGCqlvKMqUAef9jwAJNHQlqtJcndSQ7e7K g==; IronPort-SDR: u3ELgjAP/MEeZkTpB4Z70bfo5M4KC5N6tbK6ZNipWI1c7Y2poxoIkQm6Z8y3ZIophMC+c2boc5 W6nxJ1PPAUI3X0u0YQno7ZIr0oMF7q5c5tANBRNj4pcSUCDesipARP6iFin038KQh6AJv15ML7 IynOhMDyYjpdjDQ3PYbYTBNQqNdxwBq1FN3KG4uZGb64yJ+97a29oQKJ62BTbo1REAVhxclUQB +Ekd3EoRiBkY7XfABF+pBY4BZmdnxYNMvIBHVeSES/g8DCndrwFynH/sPpyOfl1Qd4MOJKzyxT K50= X-IronPort-AV: E=Sophos;i="5.81,293,1610434800"; d="scan'208";a="121233973" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 31 Mar 2021 03:59:56 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Wed, 31 Mar 2021 03:59:56 -0700 Received: from rob-dk-mpu01.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Wed, 31 Mar 2021 03:59:54 -0700 From: Claudiu Beznea To: , , , , CC: , , , Claudiu Beznea Subject: [PATCH 17/24] ARM: at91: pm: add sama7g5 ddr controller Date: Wed, 31 Mar 2021 13:59:01 +0300 Message-ID: <20210331105908.23027-18-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20210331105908.23027-1-claudiu.beznea@microchip.com> References: <20210331105908.23027-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add SAMA7G5 DDR controller to the list of DDR controller compatibles. At the moment there is no standby support. Adapt the code for this. Signed-off-by: Claudiu Beznea --- arch/arm/mach-at91/pm.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 65e13769cf50..5dc942a2012d 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -548,6 +548,7 @@ static const struct of_device_id ramc_ids[] __initconst = { { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] }, { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] }, { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] }, + { .compatible = "microchip,sama7g5-uddrc", }, { /*sentinel*/ } }; @@ -565,9 +566,11 @@ static __init void at91_dt_ramc(void) panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx); ramc = of_id->data; - if (!standby) - standby = ramc->idle; - soc_pm.data.memctrl = ramc->memctrl; + if (ramc) { + if (!standby) + standby = ramc->idle; + soc_pm.data.memctrl = ramc->memctrl; + } idx++; }