diff mbox series

[14/16] dt-bindings: phy: Convert Cadence DPHY binding to YAML

Message ID 20210330173348.30135-15-p.yadav@ti.com
State Superseded
Headers show
Series CSI2RX support on J721E | expand

Commit Message

Pratyush Yadav March 30, 2021, 5:33 p.m. UTC
Convert Cadence DPHY binding to YAML.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
---
 .../devicetree/bindings/phy/cdns,dphy.txt     | 20 --------
 .../devicetree/bindings/phy/cdns,dphy.yaml    | 51 +++++++++++++++++++
 2 files changed, 51 insertions(+), 20 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy.txt
 create mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy.yaml

Comments

Laurent Pinchart April 2, 2021, 10:23 a.m. UTC | #1
Hi Pratyush,

Thank you for the patch.

On Tue, Mar 30, 2021 at 11:03:46PM +0530, Pratyush Yadav wrote:
> Convert Cadence DPHY binding to YAML.

> 

> Signed-off-by: Pratyush Yadav <p.yadav@ti.com>

> ---

>  .../devicetree/bindings/phy/cdns,dphy.txt     | 20 --------

>  .../devicetree/bindings/phy/cdns,dphy.yaml    | 51 +++++++++++++++++++

>  2 files changed, 51 insertions(+), 20 deletions(-)

>  delete mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy.txt

>  create mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy.yaml

> 

> diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.txt b/Documentation/devicetree/bindings/phy/cdns,dphy.txt

> deleted file mode 100644

> index 1095bc4e72d9..000000000000

> --- a/Documentation/devicetree/bindings/phy/cdns,dphy.txt

> +++ /dev/null

> @@ -1,20 +0,0 @@

> -Cadence DPHY

> -============

> -

> -Cadence DPHY block.

> -

> -Required properties:

> -- compatible: should be set to "cdns,dphy".

> -- reg: physical base address and length of the DPHY registers.

> -- clocks: DPHY reference clocks.

> -- clock-names: must contain "psm" and "pll_ref".

> -- #phy-cells: must be set to 0.

> -

> -Example:

> -	dphy0: dphy@fd0e0000{

> -		compatible = "cdns,dphy";

> -		reg = <0x0 0xfd0e0000 0x0 0x1000>;

> -		clocks = <&psm_clk>, <&pll_ref_clk>;

> -		clock-names = "psm", "pll_ref";

> -		#phy-cells = <0>;

> -	};

> diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml

> new file mode 100644

> index 000000000000..d1bbf96a8250

> --- /dev/null

> +++ b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml

> @@ -0,0 +1,51 @@

> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

> +%YAML 1.2

> +---

> +$id: http://devicetree.org/schemas/phy/cdns,dphy.yaml#

> +$schema: http://devicetree.org/meta-schemas/core.yaml#

> +

> +title: Cadence DPHY Device Tree Bindings

> +

> +maintainers:

> +  - Pratyush Yadav <p.yadav@ti.com>

> +

> +properties:

> +  compatible:

> +    items:

> +      - const: cdns,dphy

> +

> +  reg:

> +    maxItems: 1

> +    description: Physical base address and length of the DPHY registers.


You can drop the description.

> +

> +  clocks:

> +    maxItems: 2

> +    description: DPHY reference clocks.


It's best to describe individual items, which will then allow dropping
the maxItems property:

  clocks:
    items:
      - description: Description of the psm clock
      - description: Description of the pll_ref clock

> +

> +  clock-names:

> +    items:

> +      - const: psm

> +      - const: pll_ref

> +

> +  "#phy-cells":

> +    const: 0

> +

> +required:

> +  - compatible

> +  - reg

> +  - clocks

> +  - clock-names

> +  - "#phy-cells"

> +

> +additionalProperties: false

> +

> +examples:

> +  - |

> +

> +    dphy0: dphy@fd0e0000{


This is copied verbatim from the existing description, but while at it,
I'd rename the node from dphy@... to phy@..., as DT node are supposed to
be named according to the class of devices, not the specific device
type.

With these small issues addressed,

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>


> +        compatible = "cdns,dphy";

> +        reg = <0xfd0e0000 0x1000>;

> +        clocks = <&psm_clk>, <&pll_ref_clk>;

> +        clock-names = "psm", "pll_ref";

> +        #phy-cells = <0>;

> +    };


-- 
Regards,

Laurent Pinchart
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.txt b/Documentation/devicetree/bindings/phy/cdns,dphy.txt
deleted file mode 100644
index 1095bc4e72d9..000000000000
--- a/Documentation/devicetree/bindings/phy/cdns,dphy.txt
+++ /dev/null
@@ -1,20 +0,0 @@ 
-Cadence DPHY
-============
-
-Cadence DPHY block.
-
-Required properties:
-- compatible: should be set to "cdns,dphy".
-- reg: physical base address and length of the DPHY registers.
-- clocks: DPHY reference clocks.
-- clock-names: must contain "psm" and "pll_ref".
-- #phy-cells: must be set to 0.
-
-Example:
-	dphy0: dphy@fd0e0000{
-		compatible = "cdns,dphy";
-		reg = <0x0 0xfd0e0000 0x0 0x1000>;
-		clocks = <&psm_clk>, <&pll_ref_clk>;
-		clock-names = "psm", "pll_ref";
-		#phy-cells = <0>;
-	};
diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml
new file mode 100644
index 000000000000..d1bbf96a8250
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml
@@ -0,0 +1,51 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/cdns,dphy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence DPHY Device Tree Bindings
+
+maintainers:
+  - Pratyush Yadav <p.yadav@ti.com>
+
+properties:
+  compatible:
+    items:
+      - const: cdns,dphy
+
+  reg:
+    maxItems: 1
+    description: Physical base address and length of the DPHY registers.
+
+  clocks:
+    maxItems: 2
+    description: DPHY reference clocks.
+
+  clock-names:
+    items:
+      - const: psm
+      - const: pll_ref
+
+  "#phy-cells":
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+
+    dphy0: dphy@fd0e0000{
+        compatible = "cdns,dphy";
+        reg = <0xfd0e0000 0x1000>;
+        clocks = <&psm_clk>, <&pll_ref_clk>;
+        clock-names = "psm", "pll_ref";
+        #phy-cells = <0>;
+    };