From patchwork Thu Mar 18 11:34:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 404171 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0CD0C433E6 for ; Thu, 18 Mar 2021 11:35:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7E91F64F38 for ; Thu, 18 Mar 2021 11:35:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229908AbhCRLfG (ORCPT ); Thu, 18 Mar 2021 07:35:06 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:41602 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229931AbhCRLez (ORCPT ); Thu, 18 Mar 2021 07:34:55 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 12IBYm2J052924; Thu, 18 Mar 2021 06:34:48 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1616067288; bh=pQp9TdiWFXFmbvvfkvhvwWm/3WqsaJmINLKWXONFnxE=; h=From:To:CC:Subject:Date; b=PIYPgAP0X3td1IeDQEBS9vJVP+XqEHoROr6zrwxIXxdWJE21rqVX7+ljRAzWeo8F/ amdUl42ekD9IMrVyf1ggyJolIOYOxuTmqldAPmlDDcQMgsWVvfZTjYlPMXQiaaoS4A 9R+JEsBT0SxoQG/RYU+XBGFNkhYZoAVpfku8BASQ= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 12IBYmW4092348 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 18 Mar 2021 06:34:48 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Thu, 18 Mar 2021 06:34:48 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Thu, 18 Mar 2021 06:34:48 -0500 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 12IBYjtV077067; Thu, 18 Mar 2021 06:34:46 -0500 From: Vignesh Raghavendra To: Nishanth Menon , Tero Kristo CC: Rob Herring , , , , Vignesh Raghavendra Subject: [RESEND PATCH] arm64: dts: ti: k3-am64-main: Add ADC nodes Date: Thu, 18 Mar 2021 17:04:43 +0530 Message-ID: <20210318113443.20036-1-vigneshr@ti.com> X-Mailer: git-send-email 2.31.0 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org AM64 SoC has a single ADC IP with 8 channels. Add DT node for the same. Default usecase is to control ADC from non Linux core on the system on AM642 GP EVM, therefore mark the node as reserved in k3-am642-evm.dts file. ADC lines are not pinned out on AM642 SK board, therefore disable the node in k3-am642-sk.dts file. Signed-off-by: Vignesh Raghavendra Reviewed-by: Lokesh Vutla --- Rebase onto latest k3-dts-next: v1: lore.kernel.org/r/20210309130708.12391-1-vigneshr@ti.com Do note that dtbs_check warns about having the bindings converted to YAML which is in my future TODO list. arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 17 +++++++++++++++++ arch/arm64/boot/dts/ti/k3-am642-evm.dts | 5 +++++ arch/arm64/boot/dts/ti/k3-am642-sk.dts | 4 ++++ 3 files changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 7e7997e3adff..dc852f63d1a2 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -521,4 +521,21 @@ usb0: usb@f400000{ dr_mode = "otg"; }; }; + + tscadc0: tscadc@28001000 { + compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; + reg = <0x00 0x28001000 0x00 0x1000>; + interrupts = ; + power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 0 0>; + assigned-clocks = <&k3_clks 0 0>; + assigned-clock-parents = <&k3_clks 0 3>; + assigned-clock-rates = <60000000>; + clock-names = "adc_tsc_fck"; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am654-adc", "ti,am3359-adc"; + }; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 1365e3164294..6331fd426157 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -377,3 +377,8 @@ cpsw3g_phy0: ethernet-phy@0 { ti,fifo-depth = ; }; }; + +&tscadc0 { + /* ADC is reserved for R5 usage */ + status = "reserved"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 397ed3b2e121..8f9b1078b7b5 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -244,3 +244,7 @@ cpsw3g_phy1: ethernet-phy@1 { ti,fifo-depth = ; }; }; + +&tscadc0 { + status = "disabled"; +};