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[23.128.96.18]) by mx.google.com with ESMTP id t3si4576077ejy.142.2021.03.10.07.47.47; Wed, 10 Mar 2021 07:47:47 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=FgC6uoBU; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233366AbhCJPrP (ORCPT + 6 others); Wed, 10 Mar 2021 10:47:15 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:43942 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233295AbhCJPqu (ORCPT ); Wed, 10 Mar 2021 10:46:50 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 12AFkjNt117466; Wed, 10 Mar 2021 09:46:45 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1615391205; bh=IjE4+sVmj9b7uWH0Qtl4puH2vI4xiCmim5sz8gnjpRs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=FgC6uoBUreTHp+8eOpQJpXtkZM9dJGZowd/DXtmIwjkcvOOnFHKdFEN+6w2UuF/3k xjbNPVgFSQex1Jbr94Lfckx2GZH++9eJpts86h1WCN7TVSEZ+LEY97cl3OHD2rgOsq Ls1IF49Hqg0dxOE2vsrtWVpgke9WPwSIp9bppxyg= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 12AFkjs8088758 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 10 Mar 2021 09:46:45 -0600 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 10 Mar 2021 09:46:45 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 10 Mar 2021 09:46:45 -0600 Received: from a0393678-ssd.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 12AFk2Kb066370; Wed, 10 Mar 2021 09:46:43 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Philipp Zabel , Swapnil Jakhade CC: , , Lokesh Vutla Subject: [PATCH v6 13/13] phy: cadence: sierra: Enable pll_cmnlc and pll_cmnlc1 clocks Date: Wed, 10 Mar 2021 21:15:58 +0530 Message-ID: <20210310154558.32078-14-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210310154558.32078-1-kishon@ti.com> References: <20210310154558.32078-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Get pll_cmnlc and pll_cmnlc1 optional clocks and enable them. This will enable REFRCV/1 in case the pll_cmnlc/1 takes input from REFRCV/1 respectively. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 40 ++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 3 deletions(-) -- 2.17.1 Reviewed-by: Swapnil Jakhade diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 039ca10db59d..5c68e31c5939 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -768,6 +768,40 @@ static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, return 0; } +static int cdns_sierra_phy_enable_clocks(struct cdns_sierra_phy *sp) +{ + int ret; + + ret = clk_prepare_enable(sp->input_clks[PHY_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]); + if (ret) + goto err_pll_cmnlc; + + ret = clk_prepare_enable(sp->output_clks[CDNS_SIERRA_PLL_CMNLC1]); + if (ret) + goto err_pll_cmnlc1; + + return 0; + +err_pll_cmnlc1: + clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]); + +err_pll_cmnlc: + clk_disable_unprepare(sp->input_clks[PHY_CLK]); + + return ret; +} + +static void cdns_sierra_phy_disable_clocks(struct cdns_sierra_phy *sp) +{ + clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC1]); + clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]); + clk_disable_unprepare(sp->input_clks[PHY_CLK]); +} + static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp, struct device *dev) { @@ -848,7 +882,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) if (ret) goto unregister_clk; - ret = clk_prepare_enable(sp->input_clks[PHY_CLK]); + ret = cdns_sierra_phy_enable_clocks(sp); if (ret) goto unregister_clk; @@ -925,7 +959,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) reset_control_put(sp->phys[i].lnk_rst); of_node_put(child); clk_disable: - clk_disable_unprepare(sp->input_clks[PHY_CLK]); + cdns_sierra_phy_disable_clocks(sp); reset_control_assert(sp->apb_rst); unregister_clk: cdns_sierra_clk_unregister(sp); @@ -941,6 +975,7 @@ static int cdns_sierra_phy_remove(struct platform_device *pdev) reset_control_assert(phy->apb_rst); pm_runtime_disable(&pdev->dev); + cdns_sierra_phy_disable_clocks(phy); /* * The device level resets will be put automatically. * Need to put the subnode resets here though. @@ -950,7 +985,6 @@ static int cdns_sierra_phy_remove(struct platform_device *pdev) reset_control_put(phy->phys[i].lnk_rst); } - clk_disable_unprepare(phy->input_clks[PHY_CLK]); cdns_sierra_clk_unregister(phy); return 0;