From patchwork Wed Mar 10 05:25:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 397892 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AB2DC43333 for ; Wed, 10 Mar 2021 05:26:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EEE8864FF4 for ; Wed, 10 Mar 2021 05:26:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232320AbhCJF0S (ORCPT ); Wed, 10 Mar 2021 00:26:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54878 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232324AbhCJF0D (ORCPT ); Wed, 10 Mar 2021 00:26:03 -0500 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3270AC061761 for ; Tue, 9 Mar 2021 21:26:03 -0800 (PST) Received: by mail-pl1-x62b.google.com with SMTP id j6so7900742plx.6 for ; Tue, 09 Mar 2021 21:26:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MyRCvPaVcQpraU+Ca0FoAU2tyJOU/YwufLj6r26LxEI=; b=D6lyYhKUOzYxKJP9wW1OlrsACoqZ0od54Zu2hf1RH5ThM8X+8haQ322vVyG0VgGYG8 a3OvxE2iPvBMOand9IusfG8625ACzjFrUixK3WHIif4P951pozwIY85ijfSiSPPjkPmq hJqSd/n8HdGW68p3z0QW0LUgDbDlrte3gxd3M/NWvUhDJVQ2KPSaCDFaws6YNWUxg0rY tagg1+7vwkHCLiZ6weBdJhTmhavbvgLhu2TCKMLZeNGHa2o6aXHlczxFoVAjgYoUveKv mkVBqmB+ffwF6l49jMrZmLQbuEP++cdfYQtCBkosOQHoqdGBnNc3uDaqwXOs4z73XnLQ nQ9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MyRCvPaVcQpraU+Ca0FoAU2tyJOU/YwufLj6r26LxEI=; b=jPiGtNlI3vtGaOUNRvsUtzRKApWmDAaG2nNDauDpjM6Ia8quXW7JryFObT840q1DuV E3bkyXXxfsQ6OjovK2jN+PsU2zrI1307ZtTdqPAt85kx+WK0lAvpWfjiqerHdydR5ERB zB7tw7JvyB7zWldiTLVcNb+v3Qrx65AqCpAlEDsw5mN4ozNox2prqplUsR1tkocQ+g4s HuMJBF+X5WsuQkwW29WBtFcSvgNFAET9e7iUxPrDTb9Vj6BppJuIOGQU3RWwSR9+/XnT wi7Q7NKS25a0hMhxdknFvzQcTlLTljAj6eg06R5/X7oZPtMY/DQ2yQpaOmh22knt+sYH SQLQ== X-Gm-Message-State: AOAM531dnmzVLVLtsth86JIUhvTqGwgL04cuFZX7WUEckhtY0VxiZrvx V+ZubRktD9nCJHLBp4RUzCxMbw== X-Google-Smtp-Source: ABdhPJz3/IVhZZduaRV272ANjvrN6PpFXwgaoJQOGccIirWhB2t2MT3WW+JVnlbUGlhy+GyZuy3QzA== X-Received: by 2002:a17:90a:987:: with SMTP id 7mr1729387pjo.97.1615353962846; Tue, 09 Mar 2021 21:26:02 -0800 (PST) Received: from localhost.localdomain ([2402:3a80:9f4:a436:21bd:7573:25c0:73a0]) by smtp.gmail.com with ESMTPSA id g7sm13915224pgb.10.2021.03.09.21.25.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Mar 2021 21:26:02 -0800 (PST) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org Cc: bhupesh.sharma@linaro.org, Vinod Koul , Thara Gopinath , Bjorn Andersson , Rob Herring , Andy Gross , Herbert Xu , "David S . Miller" , Stephen Boyd , Michael Turquette , linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH 6/8] clk: qcom: Add gcc clocks for crypto block on sm8250 Date: Wed, 10 Mar 2021 10:55:01 +0530 Message-Id: <20210310052503.3618486-7-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210310052503.3618486-1-bhupesh.sharma@linaro.org> References: <20210310052503.3618486-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds the global clock controller (gcc) clocks required by the sm8250 crypto block to function, namely: GCC_CE1_AHB_CLK, GCC_CE1_AXI_CLK and GCC_CE1_CLK. Cc: Vinod Koul Cc: Thara Gopinath Cc: Bjorn Andersson Cc: Rob Herring Cc: Andy Gross Cc: Herbert Xu Cc: David S. Miller Cc: Stephen Boyd Cc: Michael Turquette Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma --- drivers/clk/qcom/gcc-sm8250.c | 44 +++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/clk/qcom/gcc-sm8250.c b/drivers/clk/qcom/gcc-sm8250.c index ab594a0f0c40..0df5ac346c93 100644 --- a/drivers/clk/qcom/gcc-sm8250.c +++ b/drivers/clk/qcom/gcc-sm8250.c @@ -1198,6 +1198,47 @@ static struct clk_branch gcc_camera_xo_clk = { }, }; +static struct clk_branch gcc_ce1_ahb_clk = { + .halt_reg = 0x4100c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x4100c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(3), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ce1_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ce1_axi_clk = { + .halt_reg = 0x41008, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ce1_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ce1_clk = { + .halt_reg = 0x41004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(5), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ce1_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { .halt_reg = 0xf07c, .halt_check = BRANCH_HALT_VOTED, @@ -3325,6 +3366,9 @@ static struct clk_regmap *gcc_sm8250_clocks[] = { [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, + [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, + [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, + [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,