From patchwork Tue Mar 9 13:07:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 396974 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48EC0C433E0 for ; Tue, 9 Mar 2021 13:08:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 11E1F65287 for ; Tue, 9 Mar 2021 13:08:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231149AbhCINHw (ORCPT ); Tue, 9 Mar 2021 08:07:52 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:33538 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230492AbhCINHm (ORCPT ); Tue, 9 Mar 2021 08:07:42 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 129D7Z7c006430; Tue, 9 Mar 2021 07:07:35 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1615295255; bh=H4KLeRcY8FYKwED6Dp8oQb+JI73HrNZNMg+0rhkPUEg=; h=From:To:CC:Subject:Date; b=I1ExK8yrkG7qJ0zpY2RYoVFSJwAKWSwmBVqNwPvFuvH9mHg2GCc3X/cBN9OcbCCtg AWBFT3I0lRzYEJ9CjSDzzaadRSzpWTszX8Hs7MtsR7lKDRJiA6reQf4lSe6i6oZmcI 9VN/qnPOusp577VkOg5PX4JE44VjsrKwfKFbh5t0= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 129D7ZUn125097 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 9 Mar 2021 07:07:35 -0600 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 9 Mar 2021 07:07:35 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Tue, 9 Mar 2021 07:07:35 -0600 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 129D7Vgb098032; Tue, 9 Mar 2021 07:07:32 -0600 From: Vignesh Raghavendra To: Nishanth Menon , Tero Kristo CC: Rob Herring , , , , Vignesh Raghavendra , Lokesh Vutla Subject: [PATCH] arm64: dts: ti: k3-am64-main: Add ADC nodes Date: Tue, 9 Mar 2021 18:37:08 +0530 Message-ID: <20210309130708.12391-1-vigneshr@ti.com> X-Mailer: git-send-email 2.30.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org AM64 SoC has a single ADC IP with 8 channels. Add DT node for the same. Default usecase is to control ADC from non Linux core on the system on AM642 GP EVM, therefore mark the node as reserved in k3-am642-evm.dts file. ADC lines are not pinned out on AM642 SK board, therefore disable the node in k3-am642-sk.dts file. Signed-off-by: Vignesh Raghavendra Reviewed-by: Lokesh Vutla --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 17 +++++++++++++++++ arch/arm64/boot/dts/ti/k3-am642-evm.dts | 5 +++++ arch/arm64/boot/dts/ti/k3-am642-sk.dts | 4 ++++ 3 files changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index bcec4fa444b5..1bb1e292547d 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -427,4 +427,21 @@ ospi0: spi@fc40000 { power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; }; }; + + tscadc0: tscadc@28001000 { + compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; + reg = <0x00 0x28001000 0x00 0x1000>; + interrupts = ; + power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 0 0>; + assigned-clocks = <&k3_clks 0 0>; + assigned-clock-parents = <&k3_clks 0 3>; + assigned-clock-rates = <60000000>; + clock-names = "adc_tsc_fck"; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am654-adc", "ti,am3359-adc"; + }; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 7dd8e94b108d..7154d34faf4c 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -280,3 +280,8 @@ flash@0{ #size-cells = <1>; }; }; + +&tscadc0 { + /* ADC is reserved for R5 usage */ + status = "reserved"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index fc27470fc083..28059f07bef1 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -207,3 +207,7 @@ flash@0{ #size-cells = <1>; }; }; + +&tscadc0 { + status = "disabled"; +};