From patchwork Mon Mar 8 05:07:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 395341 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp1422564jai; Sun, 7 Mar 2021 21:10:27 -0800 (PST) X-Google-Smtp-Source: ABdhPJzbnmg4giTUWaapxkeqzWB+2hV/3EcglC1TtjhMdLYxBqezRNM+IydwOGCxNal7Y4ni+M/x X-Received: by 2002:a17:907:2d9f:: with SMTP id gt31mr13324202ejc.233.1615180227789; Sun, 07 Mar 2021 21:10:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615180227; cv=none; d=google.com; s=arc-20160816; b=pRRoDw2MJn7j2C2B0TclLWlNZ3v/ZeNASdTZFBx2iNpUGi6h+Mnr+u4Mfg3/4MEet6 m7idO4vIanogEKpmZ9ClDEn4O2Vc/wNtBCkRJFNlAgiRAG5vtrVKtf04lxxgktyLM1ML DKfnYfrcU40PMYuXlhsa3e+GGa2dTlBeL74gNtbbo2LdNp5vhzCqVB4tVKGHTT4UmoN0 DQeRyt3Jam8EmFu5FnvB4sU5VRSbjaspCpyUal6mgp+6Gw2rGe2H3mxIhX90MbDIREDe CQ0rGGdi0hw7zqRSql9urtZFJxCP345Nbo/VRI6jSO2y/IwZhF9mlWn2C7GWvwYDh0m0 AtVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=+Y00hdZP+qH3GUjqo1BgTa5yanHKcZM8l+fdCNkwrBk=; b=Dh/Zuiju8ZfDXg5y3bPOcR3lDIw5mC6Jh2UYRhv3OMQ9lhjW0Tf0mNQvkxVpR0EYke lADgEfqxPePOMlWdk/qxqQNK6Ea5E4d/NvuoWI88j0EMXi2kbh7tkGepYV4ofEUwm6lB gVnych74wjEfXn/K8z+QDaRHHZ7gc57XV+LV8lLmflWyf+HWa16chYFcGYZo80NYSzSw AARxTKDMu9WbYch2qtF28jpFjyYbZwiPSkhXi59lekyRxXiBmBqzA8+usC2n99lZ7FO/ HDDYemUOW+geBrXkwkSPyIJ9lX+2P6lKpshtwHaXrD0HaX7v+bP9BlZ9Za2q7YZSb3+t RM7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=gA3eY+1+; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id dg23si6340931edb.519.2021.03.07.21.10.27; Sun, 07 Mar 2021 21:10:27 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=gA3eY+1+; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234367AbhCHFIv (ORCPT + 6 others); Mon, 8 Mar 2021 00:08:51 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:36338 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234352AbhCHFIc (ORCPT ); Mon, 8 Mar 2021 00:08:32 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 12858Rar077337; Sun, 7 Mar 2021 23:08:27 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1615180107; bh=+Y00hdZP+qH3GUjqo1BgTa5yanHKcZM8l+fdCNkwrBk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=gA3eY+1+ymr21oGfHhAxPHO806Ci6caZG8eWEsHwXX2WusNGv0fVh5YbUhPqNtLJC RiJd2UYUcCD5/9umsRCObXPQHc/xPVHZxux3KCp+ix497pTWdg7B5i7FBDCTU5HbSB mT3JkH7W64HaSTGrHzfyx/w7INIrzkQ9krba7Ozg= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 12858RL2068871 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sun, 7 Mar 2021 23:08:27 -0600 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Sun, 7 Mar 2021 23:08:27 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Sun, 7 Mar 2021 23:08:27 -0600 Received: from a0393678-ssd.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 12857aLB086547; Sun, 7 Mar 2021 23:08:24 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Philipp Zabel , Swapnil Jakhade CC: , , Lokesh Vutla Subject: [PATCH v5 13/13] phy: cadence: sierra: Enable pll_cmnlc and pll_cmnlc1 clocks Date: Mon, 8 Mar 2021 10:37:32 +0530 Message-ID: <20210308050732.7140-14-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210308050732.7140-1-kishon@ti.com> References: <20210308050732.7140-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Get pll_cmnlc and pll_cmnlc1 optional clocks and enable them. This will enable REFRCV/1 in case the pll_cmnlc/1 takes input from REFRCV/1 respectively. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 40 ++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index b80afc11dd5c..16adc6dff04e 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -768,6 +768,40 @@ static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, return 0; } +static int cdns_sierra_phy_enable_clocks(struct cdns_sierra_phy *sp) +{ + int ret; + + ret = clk_prepare_enable(sp->input_clks[PHY_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]); + if (ret) + goto err_pll_cmnlc; + + ret = clk_prepare_enable(sp->output_clks[CDNS_SIERRA_PLL_CMNLC1]); + if (ret) + goto err_pll_cmnlc1; + + return 0; + +err_pll_cmnlc: + clk_disable_unprepare(sp->input_clks[PHY_CLK]); + +err_pll_cmnlc1: + clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]); + + return ret; +} + +static void cdns_sierra_phy_disable_clocks(struct cdns_sierra_phy *sp) +{ + clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC1]); + clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]); + clk_disable_unprepare(sp->input_clks[PHY_CLK]); +} + static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp, struct device *dev) { @@ -848,7 +882,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) if (ret) goto unregister_clk; - ret = clk_prepare_enable(sp->input_clks[PHY_CLK]); + ret = cdns_sierra_phy_enable_clocks(sp); if (ret) goto unregister_clk; @@ -925,7 +959,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) reset_control_put(sp->phys[i].lnk_rst); of_node_put(child); clk_disable: - clk_disable_unprepare(sp->input_clks[PHY_CLK]); + cdns_sierra_phy_disable_clocks(sp); reset_control_assert(sp->apb_rst); unregister_clk: cdns_sierra_clk_unregister(sp); @@ -941,6 +975,7 @@ static int cdns_sierra_phy_remove(struct platform_device *pdev) reset_control_assert(phy->apb_rst); pm_runtime_disable(&pdev->dev); + cdns_sierra_phy_disable_clocks(phy); /* * The device level resets will be put automatically. * Need to put the subnode resets here though. @@ -950,7 +985,6 @@ static int cdns_sierra_phy_remove(struct platform_device *pdev) reset_control_put(phy->phys[i].lnk_rst); } - clk_disable_unprepare(phy->input_clks[PHY_CLK]); cdns_sierra_clk_unregister(phy); return 0;