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[23.128.96.18]) by mx.google.com with ESMTP id k6si527757edj.545.2021.03.04.14.27.18; Thu, 04 Mar 2021 14:27:19 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=v64pJ8M3; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240032AbhCDMHT (ORCPT + 6 others); Thu, 4 Mar 2021 07:07:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60012 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240104AbhCDMHD (ORCPT ); Thu, 4 Mar 2021 07:07:03 -0500 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63BFBC0613BF for ; Thu, 4 Mar 2021 04:06:06 -0800 (PST) Received: by mail-ej1-x629.google.com with SMTP id ci14so29844412ejc.7 for ; Thu, 04 Mar 2021 04:06:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7gB7AoMOiyCQb9quZTWnXT3iMQcjF/gibktg5jIRWV4=; b=v64pJ8M3YDB+r6KM9ZQl+aVsu7WYQ0ZHFmse3A61Q19/oNYREkI0lffRf9+6ppv+pP 42fSWI1g+APc4Q2u9BQ27HvGDqDaVfD17gm004rNDtIXYhG6KTKnCm5X8kL+rxtSb1Sy uSOrxkD+gS69IbSdDKOKOheheIibus07gUx8VzJpOSlZ3jHQc6owYc7nSstnO8xpQ8Of F6F5x2ON+1bT5+8cdiTi//iitVHz+/huZjMU1zC4lYRGZezzE2m7DykNJxk3K1rxFnWq BNm/dD3tWw1xYoRseQjdcxK0OTrGPWLUcttQcjbJ6JmplGOl1r67Fr3bOc/O/yXLmckH TfZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7gB7AoMOiyCQb9quZTWnXT3iMQcjF/gibktg5jIRWV4=; b=GYbckWPFDG+2ZVUON1YsCn7bfTq16Xo9bfT6ctKokcj7VYq5I0x9dYMuA9YR2xaAZq B593RWdI/RTn0kYCqX4RfaK7DKDnG0j4Zij2q6KRN6PSCohFG2LpRvXfkeUyQbph+yOm 8n0VHbi724Pr9nwsJn1QOXTDKXAugVEEuCaXEpaxx1ytmMcznfkPgBYZw/K83gTtNiSL wpYfi4D5qeYOdyTU+dvQQ9GpBWILa0hFYGPv0D5BCEjS3jGsTvdJhtHGk44OsyRxzFdN VLs5n3OfK0EYigcHvLrpqB8zBEwdMp5kShXyiM85Gi/w68sCaemPUyodIw6clXYq1M1h EcuA== X-Gm-Message-State: AOAM531NV+VR0rRTzuPV2YanTbUNtuAGim7SHX+xX/aHkbDKzqHprcVo sJMvvlsL8oqBmj8PjynjTihTiA== X-Received: by 2002:a17:907:6005:: with SMTP id fs5mr3888299ejc.184.1614859565135; Thu, 04 Mar 2021 04:06:05 -0800 (PST) Received: from localhost.localdomain ([2a02:2450:102f:d6a:470a:340b:1b:29dd]) by smtp.gmail.com with ESMTPSA id cf6sm20464447edb.92.2021.03.04.04.06.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Mar 2021 04:06:04 -0800 (PST) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, robert.foss@linaro.org, todor.too@gmail.com, mchehab@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@somainline.org, linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno , Sakari Ailus , Andrey Konovalov Cc: Rob Herring , Tomasz Figa , Azam Sadiq Pasha Kapatrala Syed , Sarvesh Sridutt , Laurent Pinchart , Jonathan Marek Subject: [PATCH v6 20/22] arm64: dts: sdm845: Add CAMSS ISP node Date: Thu, 4 Mar 2021 13:03:26 +0100 Message-Id: <20210304120326.153966-21-robert.foss@linaro.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210304120326.153966-1-robert.foss@linaro.org> References: <20210304120326.153966-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the camss dt node for sdm845. Signed-off-by: Robert Foss Reviewed-by: Andrey Konovalov --- Changes since v1 - Laurent: Fix subject - Laurent: Remove redundant regulator labels - Laurent: Remove empty line Changes since v3 - Fixed ordering of IRQs - Add newlines for better readability Changes since v5: - Andrey: Add r-b arch/arm64/boot/dts/qcom/sdm845.dtsi | 135 +++++++++++++++++++++++++++ 1 file changed, 135 insertions(+) -- 2.27.0 diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index bcf888381f14..4fe93c69908a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3911,6 +3911,141 @@ videocc: clock-controller@ab00000 { #reset-cells = <1>; }; + camss: camss@a00000 { + compatible = "qcom,sdm845-camss"; + + reg = <0 0xacb3000 0 0x1000>, + <0 0xacba000 0 0x1000>, + <0 0xacc8000 0 0x1000>, + <0 0xac65000 0 0x1000>, + <0 0xac66000 0 0x1000>, + <0 0xac67000 0 0x1000>, + <0 0xac68000 0 0x1000>, + <0 0xacaf000 0 0x4000>, + <0 0xacb6000 0 0x4000>, + <0 0xacc4000 0 0x4000>; + reg-names = "csid0", + "csid1", + "csid2", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "vfe0", + "vfe1", + "vfe_lite"; + + interrupts = , + , + , + , + , + , + , + , + , + ; + interrupt-names = "csid0", + "csid1", + "csid2", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "vfe0", + "vfe1", + "vfe_lite"; + + power-domains = <&clock_camcc IFE_0_GDSC>, + <&clock_camcc IFE_1_GDSC>, + <&clock_camcc TITAN_TOP_GDSC>; + + clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY0_CLK>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY1_CLK>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY2_CLK>, + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY3_CLK>, + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_AXI_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_0_AXI_CLK>, + <&clock_camcc CAM_CC_IFE_0_CLK>, + <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_AXI_CLK>, + <&clock_camcc CAM_CC_IFE_1_CLK>, + <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cphy_rx_src", + "csi0", + "csi0_src", + "csi1", + "csi1_src", + "csi2", + "csi2_src", + "csiphy0", + "csiphy0_timer", + "csiphy0_timer_src", + "csiphy1", + "csiphy1_timer", + "csiphy1_timer_src", + "csiphy2", + "csiphy2_timer", + "csiphy2_timer_src", + "csiphy3", + "csiphy3_timer", + "csiphy3_timer_src", + "gcc_camera_ahb", + "gcc_camera_axi", + "slow_ahb_src", + "soc_ahb", + "vfe0_axi", + "vfe0", + "vfe0_cphy_rx", + "vfe0_src", + "vfe1_axi", + "vfe1", + "vfe1_cphy_rx", + "vfe1_src", + "vfe_lite", + "vfe_lite_cphy_rx", + "vfe_lite_src"; + + iommus = <&apps_smmu 0x0808 0x0>, + <&apps_smmu 0x0810 0x8>, + <&apps_smmu 0x0c08 0x0>, + <&apps_smmu 0x0c10 0x8>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + cci: cci@ac4a000 { compatible = "qcom,sdm845-cci"; #address-cells = <1>;