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[23.128.96.18]) by mx.google.com with ESMTP id t16si11433091ejj.217.2021.02.22.03.25.42; Mon, 22 Feb 2021 03:25:42 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=FNziTBa8; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230422AbhBVLZC (ORCPT + 6 others); Mon, 22 Feb 2021 06:25:02 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:57332 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230437AbhBVLY6 (ORCPT ); Mon, 22 Feb 2021 06:24:58 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 11MBNhxr007131; Mon, 22 Feb 2021 05:23:43 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1613993023; bh=ejNLP8A0/TozqWiIO9rw/YN3cU1wXkHRhs46676Bh+o=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=FNziTBa8jf46AudF0ZD0QI0kzHFUi+AkjCf+HVzp3lwm9ihWMFBSsMZ3HOBZW3sVD BAN2ZsN0IJSRQEuX0z/V8HYocDm+gSzcl712b+d+xRhvA75kPIXDz6D1R9pbLvkZZw b9yEtYTl/ZhNFgnE46he7cyIehH7h0nup51vwILE= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 11MBNhq0101411 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 22 Feb 2021 05:23:43 -0600 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 22 Feb 2021 05:23:42 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 22 Feb 2021 05:23:42 -0600 Received: from a0393678-ssd.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 11MBNFDc088010; Mon, 22 Feb 2021 05:23:40 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Peter Rosin , Swapnil Jakhade CC: , , Subject: [PATCH v2 3/9] dt-bindings: ti-serdes-mux: Add defines for AM64 SoC Date: Mon, 22 Feb 2021 16:53:08 +0530 Message-ID: <20210222112314.10772-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210222112314.10772-1-kishon@ti.com> References: <20210222112314.10772-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org AM64 has a single lane SERDES which can be configured to be used with either PCIe or USB. Define the possilbe values for the SERDES function in AM64 SoC here. Signed-off-by: Kishon Vijay Abraham I Acked-by: Peter Rosin --- include/dt-bindings/mux/ti-serdes.h | 5 +++++ 1 file changed, 5 insertions(+) -- 2.17.1 Acked-by: Rob Herring diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h index 9047ec6bd3cf..d417b9268b16 100644 --- a/include/dt-bindings/mux/ti-serdes.h +++ b/include/dt-bindings/mux/ti-serdes.h @@ -90,4 +90,9 @@ #define J7200_SERDES0_LANE3_USB 0x2 #define J7200_SERDES0_LANE3_IP4_UNUSED 0x3 +/* AM64 */ + +#define AM64_SERDES0_LANE0_PCIE0 0x0 +#define AM64_SERDES0_LANE0_USB 0x1 + #endif /* _DT_BINDINGS_MUX_TI_SERDES */