From patchwork Wed Feb 3 12:59:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 375556 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE921C433E0 for ; Wed, 3 Feb 2021 13:03:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 91B2764F6C for ; Wed, 3 Feb 2021 13:03:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229962AbhBCNDi (ORCPT ); Wed, 3 Feb 2021 08:03:38 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:14165 "EHLO esa2.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230151AbhBCNDh (ORCPT ); Wed, 3 Feb 2021 08:03:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1612358058; x=1643894058; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NxkrMnisgB5Y7CCjo51izxzf/ZM8UZEu9H+xpU97oZI=; b=Vc3Wg9pU8egdT78oytfMxsNkESxiloeax4PlxXO9zwF9QEUXSETIZM/Y LjbGo9avUDN3PT84LZvtjcibrhU+c/znO2aARTvH47NzAcptszW0hWp3O p+07ZPoA8oH6cOEj6HcYUNSTwbFksPEDopb42TKo9BBy0xCe6ekEL5qDZ 8E9JWgBCfMsfpAgwcoj/ui9GV9f83tMln69upvAzAyFIK7bWOhvwaZCrO SZM1aSycOs+qf1NeI+A5x0f6gXPggd1Tgig/MK6KVcxyxy7iSXlQ3jXx1 ws8gelO0wNpy7prNQpt+GC5FZiM5bjP4LamYnc0q5zL51vcJHn1reRSjS A==; IronPort-SDR: Np6Mo7KLfhr1YTpOe0JtXm4TXoxCJRQrqsem2qr3GEIAnuhwaGyyI4dhBLdxU9Wgpo11biJJyC FhmdkenA843U2njimhOjEtMuDJYUEW70Y460dD5nXzggu14QJAgxRcxPUaW8d1qYikxlfVr7tW NfwMdoTASlUUqrhhAyGzVAOtKsHfsRR0hxFKLfkKUBuDuhki4cbrXmtKlU77tQBfEDsC+CFFhH ltxnemnw67wHXXnorvzfFL+zTZ6nCvZcasRxWMglYpeCj1tXiekfVTygoRLarFAjj5ktZuMa82 QXc= X-IronPort-AV: E=Sophos;i="5.79,398,1602518400"; d="scan'208";a="263106959" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 03 Feb 2021 21:08:54 +0800 IronPort-SDR: zfvyXLBotE0OUz5Lu1/eXABfu0E6fYH3kKAO5xikSJ6SYPKUzhJpMmW6edyfkKeawG2mCwxkPJ 0DrryILAKSYy6b+tWs/kbPGCEWNjPmRgCqOtK7Mp5kvg0p0U2yg5oiRh3wthLr76jGBri3taYt bX/gRm6bRsjOrwSPEev9osZNEfLlVf8bfoDxgdqGbSAhmWu9GzXXJQUoFcOn7XyIWiVPyoyX7p UhJt5WKtNj0zcTc7x7rIiFjNr9WpyP/c1cyTxdLpRy2aHwY607YOZ6eYXyQ1BucTBrMxzFnWXH pn5kObSLdO/7sYw4OGiTpLsO Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2021 04:44:02 -0800 IronPort-SDR: 8cJ3MwjpEzrQuyv/9SpF+77Fpo9n0WpN7GHLvqKNsxq27jugfIL3Wa3WRc3z1DOwjxKcgvpQC2 nQZxO0Z532r25VyyHC1eNAN30KE0ehfkiVe2oUDGDH444zDTeo/PIRBr+Won0MULhUX8jNNEvQ KANt+mqpZxVLXLWVug+4qAga+LXDItH1m/S1MRKTy4+LLctdjmbWNXvhvEUPmRFKTpzXwC4hn+ 7QwcdYJg/hRZCn1sm7z8tauhJTTeNa3bCdwHjru76q+aB6iFHztY3objIIWUj6r6a4f9m4Ebhz NKw= WDCIronportException: Internal Received: from wdapacbjl0003.my.asia.wdc.com (HELO twashi.fujisawa.hgst.com) ([10.84.71.58]) by uls-op-cesaip01.wdc.com with ESMTP; 03 Feb 2021 05:00:00 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Atish Patra , Anup Patel , Sean Anderson , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v15 13/16] riscv: Add SiPeed MAIXDUINO board device tree Date: Wed, 3 Feb 2021 21:59:10 +0900 Message-Id: <20210203125913.390949-14-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210203125913.390949-1-damien.lemoal@wdc.com> References: <20210203125913.390949-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the device tree sipeed_maixduino.dts for the SiPeed MAIXDUINO board. This device tree enables LEDs and spi/mmc SD card device. Additionally, gpios and i2c are also enabled and mapped to the board header pins as indicated on the board itself. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal --- .../boot/dts/canaan/sipeed_maixduino.dts | 209 ++++++++++++++++++ 1 file changed, 209 insertions(+) create mode 100644 arch/riscv/boot/dts/canaan/sipeed_maixduino.dts diff --git a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts new file mode 100644 index 000000000000..804edc45eeeb --- /dev/null +++ b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-20 Sean Anderson + * Copyright (C) 2020 Western Digital Corporation or its affiliates. + */ + +/dts-v1/; + +#include "k210.dtsi" + +#include +#include + +/ { + model = "SiPeed MAIXDUINO"; + compatible = "sipeed,maixduino", "canaan,kendryte-k210"; + + chosen { + bootargs = "earlycon console=ttySIF0"; + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + boot { + label = "BOOT"; + linux,code = ; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0 0>; + }; + + simple-audio-card,codec { + sound-dai = <&mic>; + }; + }; + + mic: mic { + #sound-dai-cells = <0>; + compatible = "memsensing,msm261s4030h0"; + status = "disabled"; + }; + + vcc_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&fpioa { + status = "okay"; + + uarths_pinctrl: uarths-pinmux { + pinmux = , /* Header "0" */ + ; /* Header "1" */ + }; + + gpio_pinctrl: gpio-pinmux { + pinmux = , + ; + }; + + gpiohs_pinctrl: gpiohs-pinmux { + pinmux = , /* BOOT */ + , /* Header "2" */ + , /* Header "3" */ + , /* Header "4" */ + , /* Header "5" */ + , /* Header "6" */ + , /* Header "7" */ + , /* Header "8" */ + , /* Header "9" */ + , /* Header "10" */ + , /* Header "11" */ + , /* Header "12" */ + ; /* Header "13" */ + }; + + i2s0_pinctrl: i2s0-pinmux { + pinmux = , + , + ; + }; + + spi1_pinctrl: spi1-pinmux { + pinmux = , + , + , + ; /* cs */ + }; + + i2c1_pinctrl: i2c1-pinmux { + pinmux = , /* Header "scl" */ + ; /* Header "sda" */ + }; + + i2s1_pinctrl: i2s1-pinmux { + pinmux = , + , + ; + }; + + spi0_pinctrl: spi0-pinmux { + pinmux = , /* cs */ + , /* rst */ + , /* dc */ + ; /* wr */ + }; + + dvp_pinctrl: dvp-pinmux { + pinmux = , + , + , + , + , + , + , + ; + }; +}; + +&uarths0 { + pinctrl-0 = <&uarths_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio0 { + pinctrl-0 = <&gpiohs_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio1 { + pinctrl-0 = <&gpio_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2s0 { + #sound-dai-cells = <1>; + pinctrl-0 = <&i2s0_pinctrl>; + pinctrl-names = "default"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pinctrl>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; + +&dvp0 { + pinctrl-0 = <&dvp_pinctrl>; + pinctrl-names = "default"; +}; + +&spi0 { + pinctrl-0 = <&spi0_pinctrl>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + + panel@0 { + compatible = "sitronix,st7789v"; + reg = <0>; + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio0 22 0>; + spi-max-frequency = <15000000>; + power-supply = <&vcc_3v3>; + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_pinctrl>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio1_0 2 GPIO_ACTIVE_LOW>; + status = "okay"; + + slot@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + voltage-ranges = <3300 3300>; + spi-max-frequency = <25000000>; + broken-cd; + }; +}; + +&spi3 { + spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + broken-flash-reset; + }; +};