From patchwork Wed Jan 27 07:08:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 371484 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp4950jam; Tue, 26 Jan 2021 23:13:32 -0800 (PST) X-Google-Smtp-Source: ABdhPJzyrc0Gec/0mwhvSPMMZ1RvOlYZ0zWbSeLBmqC4VFsnL2jeYgC1dNU9VVOvAbK6A/yYiLw0 X-Received: by 2002:a05:6402:1648:: with SMTP id s8mr7784913edx.50.1611731612362; Tue, 26 Jan 2021 23:13:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611731612; cv=none; d=google.com; s=arc-20160816; b=MX3RjbDE/FMFgDkJ/23gwKyOq7j78KH6pBPVg0SL+8zZ7NeyOU1Snl4SPOB/m5UeXQ AkoelTgakfbyc1IgfYPtRakDDR58qA1y8GLbDnaheLlHSiEirEnHlI6t+IAMUd1HI99v zcWk+UilX+J9LkJ57u2K9OR/5fUiJUwXW6BQX5MWOzrQ/tJXIQORaKLPHtbMwSx2c2w/ RUGUrPMydPK+q78LytjdB+/Q2bqgmzXU/7mjs2fEbkxSJH3TWMR9VmL0ogCGBSDZF0ni aDeYCv+R4p/LBDnumdDE60PvQuJJjTD7q2+PvdN/OTcj6zJrGLcGKl+2nHhyJOSDS5Oe D4/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FAr84b657ENfqwW1xH018mrLKxVL4Tttjz3W1oTzdVU=; b=TSY7VZ/MInZHz3d+JtR5SQLykFKkNV3UVAaOGVGx210VtXnZ9yKZmlXDnwKRnMQJrk 74desocN/pf9zjZ01BCWx89sKMt4VQtCh0tC+Jk749JtXViqU1CkTKxt+fYnKVWoB0RY WlkXm1M0IvX8M2l3oC15KPgnysMioqEVeZNQ5ar0ilbq324Rb/jUvjAdcSee5U+3iXRJ xgmmjvVXuJHE9zVtoEvezqBEwaRB9t5mqG1qaxdepmEmobep3kD4G9cmr7j7ulk7E0xX TKQn0Wt+haaKMNVLcDlM0+wZF8aisGlMS+Ur7lBxSCo9QDnvBNP1FXOFiuPKRYvwOhQj bYxw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=nOPd8Wp7; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id ga16si463787ejc.412.2021.01.26.23.13.32; Tue, 26 Jan 2021 23:13:32 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=nOPd8Wp7; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233195AbhA0HMw (ORCPT + 6 others); Wed, 27 Jan 2021 02:12:52 -0500 Received: from mail.kernel.org ([198.145.29.99]:45580 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232462AbhA0HJU (ORCPT ); Wed, 27 Jan 2021 02:09:20 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 333BF2072E; Wed, 27 Jan 2021 07:08:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1611731315; bh=TXEgQVt6dpC9FtTT29E+AwUmoy6iV102b2j7ZJHxRv4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nOPd8Wp7s1/JvwdqWTz+H7QfjxACqD5kiynePuShnQw8iqKPgwyBuiKcQTga7EKw0 1Qo80IzNA56qUoc9TvuEOFBqR+Y4cgebPiOYPt6F0fkKLpmyh3kOXWkNSjBeQ02/M1 VgYUVhZyQUkwShAyuSvjWCi+it7qT/CBVVevq9s5M06yyLwdcBNhpVBJxlQk5+nnBY ZVZm9Eh38A6ryFn4MPoWN6eX8H880oIfiUQz9lOx1H/QBobRyOmC0JBwJ6JZRbgh53 v6BB+3lThQk3fnJsFpyVRHvNWirrfRr3YPksMgBYEjOanmoPuLD9WNrglzqiynFRLL FO9zOnG+F8irw== From: Vinod Koul To: Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vivek Aknurwar , Andy Gross , Michael Turquette , Rob Herring , Taniya Das , AngeloGioacchino Del Regno , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jeevan Shriram , Vinod Koul Subject: [PATCH v5 3/5] clk: qcom: clk-alpha-pll: Add support for Lucid 5LPE PLL Date: Wed, 27 Jan 2021 12:38:09 +0530 Message-Id: <20210127070811.152690-4-vkoul@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210127070811.152690-1-vkoul@kernel.org> References: <20210127070811.152690-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Vivek Aknurwar Lucid 5LPE is a slightly different Lucid PLL with different offsets and porgramming sequence so add support for these Signed-off-by: Vivek Aknurwar Signed-off-by: Jeevan Shriram [vkoul: rebase and tidy up for upstream] Signed-off-by: Vinod Koul Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Bjorn Andersson --- drivers/clk/qcom/clk-alpha-pll.c | 173 +++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 4 + 2 files changed, 177 insertions(+) -- 2.26.2 diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index a30ea7b09224..c6eb99169ddc 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -156,6 +156,12 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); /* LUCID PLL specific settings and offsets */ #define LUCID_PCAL_DONE BIT(27) +/* LUCID 5LPE PLL specific settings and offsets */ +#define LUCID_5LPE_PCAL_DONE BIT(11) +#define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13) +#define LUCID_5LPE_PLL_LATCH_INPUT BIT(14) +#define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21) + #define pll_alpha_width(p) \ ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH) @@ -1604,3 +1610,170 @@ const struct clk_ops clk_alpha_pll_agera_ops = { .set_rate = clk_alpha_pll_agera_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops); + +static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + u32 val; + int ret; + + ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); + if (ret) + return ret; + + /* If in FSM mode, just vote for it */ + if (val & LUCID_5LPE_ENABLE_VOTE_RUN) { + ret = clk_enable_regmap(hw); + if (ret) + return ret; + return wait_for_pll_enable_lock(pll); + } + + /* Check if PLL is already enabled, return if enabled */ + ret = trion_pll_is_enabled(pll, pll->clkr.regmap); + if (ret < 0) + return ret; + + ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); + if (ret) + return ret; + + regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN); + + ret = wait_for_pll_enable_lock(pll); + if (ret) + return ret; + + /* Enable the PLL outputs */ + ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); + if (ret) + return ret; + + /* Enable the global PLL outputs */ + return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); +} + +static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + u32 val; + int ret; + + ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); + if (ret) + return; + + /* If in FSM mode, just unvote it */ + if (val & LUCID_5LPE_ENABLE_VOTE_RUN) { + clk_disable_regmap(hw); + return; + } + + /* Disable the global PLL output */ + ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); + if (ret) + return; + + /* Disable the PLL outputs */ + ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); + if (ret) + return; + + /* Place the PLL mode in STANDBY */ + regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY); +} + +/* + * The Lucid 5LPE PLL requires a power-on self-calibration which happens + * when the PLL comes out of reset. Calibrate in case it is not completed. + */ +static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + struct clk_hw *p; + u32 val = 0; + int ret; + + /* Return early if calibration is not needed. */ + regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); + if (val & LUCID_5LPE_PCAL_DONE) + return 0; + + p = clk_hw_get_parent(hw); + if (!p) + return -EINVAL; + + ret = alpha_pll_lucid_5lpe_enable(hw); + if (ret) + return ret; + + alpha_pll_lucid_5lpe_disable(hw); + + return 0; +} + +static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate) +{ + return __alpha_pll_trion_set_rate(hw, rate, prate, + LUCID_5LPE_PLL_LATCH_INPUT, + LUCID_5LPE_ALPHA_PLL_ACK_LATCH); +} + +static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); + int i, val = 0, div, ret; + u32 mask; + + /* + * If the PLL is in FSM mode, then treat set_rate callback as a + * no-operation. + */ + ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); + if (ret) + return ret; + + if (val & LUCID_5LPE_ENABLE_VOTE_RUN) + return 0; + + div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); + for (i = 0; i < pll->num_post_div; i++) { + if (pll->post_div_table[i].div == div) { + val = pll->post_div_table[i].val; + break; + } + } + + mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift); + return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), + mask, val << pll->post_div_shift); +} + +const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = { + .prepare = alpha_pll_lucid_5lpe_prepare, + .enable = alpha_pll_lucid_5lpe_enable, + .disable = alpha_pll_lucid_5lpe_disable, + .is_enabled = clk_trion_pll_is_enabled, + .recalc_rate = clk_trion_pll_recalc_rate, + .round_rate = clk_alpha_pll_round_rate, + .set_rate = alpha_pll_lucid_5lpe_set_rate, +}; +EXPORT_SYMBOL(clk_alpha_pll_lucid_5lpe_ops); + +const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = { + .enable = alpha_pll_lucid_5lpe_enable, + .disable = alpha_pll_lucid_5lpe_disable, + .is_enabled = clk_trion_pll_is_enabled, + .recalc_rate = clk_trion_pll_recalc_rate, + .round_rate = clk_alpha_pll_round_rate, +}; +EXPORT_SYMBOL(clk_alpha_pll_fixed_lucid_5lpe_ops); + +const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = { + .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, + .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, + .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate, +}; +EXPORT_SYMBOL(clk_alpha_pll_postdiv_lucid_5lpe_ops); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 0ea30d2f3da1..6943e933be0f 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -144,6 +144,10 @@ extern const struct clk_ops clk_alpha_pll_lucid_ops; extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops; extern const struct clk_ops clk_alpha_pll_agera_ops; +extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops; +extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops; +extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops; + void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,