From patchwork Wed Jan 20 13:43:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 368148 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A4A7C0044D for ; Wed, 20 Jan 2021 21:09:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D51CB2343E for ; Wed, 20 Jan 2021 21:09:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731651AbhATUz6 (ORCPT ); Wed, 20 Jan 2021 15:55:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44616 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389171AbhATNu7 (ORCPT ); Wed, 20 Jan 2021 08:50:59 -0500 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 38039C061349 for ; Wed, 20 Jan 2021 05:44:59 -0800 (PST) Received: by mail-wr1-x42a.google.com with SMTP id a1so1853195wrq.6 for ; Wed, 20 Jan 2021 05:44:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+loFyb/XyYA9+SNeFfqDGg8zUbSf9smApXbMMlw/g1k=; b=l3UdpfRimrmV+9OH1O+9APRN9dkQYDYm0hvP+PedUaouy6w2SwWuDq41fcGWDQs97S ubbKJcZRt0bG20jKBwz311QPjUzzuNsXY7noXvnZx6qlxnT9xjF7puATladtv6XSWeH3 bBGKCY7qtOoEVb07idWcMMgez4AEEQ7iNqyYxHYo5NJvActK5K6pDuDNQ7dGbblt9rZ2 fIgmu3Am/jot3uXmElmA50R37bDwTvlS7veNA7jZzuc73hhiusSocISpJILqF+Nk4ixi J31VNf7+Tbq16LO8Ii4KmPG5BZw5GcxbcAC9dKvtRyyi2Bx28rAOH2SDY/wUDj41f1IY MEVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+loFyb/XyYA9+SNeFfqDGg8zUbSf9smApXbMMlw/g1k=; b=VloT9EZoiERm89vsxf6K7GLOQ5IV7JFq0npinYkKGJdL8/i7BhKbOvLK7o24D5uWZA MdYEnVAsOYAqnurLO1GvrVJbkH8YlQBHL7z2oRQbQ2Jy6DOs1xPh4GcyMvf24Ir6crqC wpUGOjz10d1J5vVN00AVlcisfhxJrxIa5g4c8kqFjNrfjfQeXHE662o+TLN6nuM6Uxlp f58ZDzsZZofocLHjoUY9s+xhnt2KIaTEO5AqsTxLH1I1nUsAIek/cFKqrTap9LvrokjZ rcUgARMHKoM+PTiBAQ177Anwt8TRwOgZMIaQ5peANFaqQ3G5GyPtX99XCAhGV0s8vrqT k++Q== X-Gm-Message-State: AOAM531241uGQ9BDqI6PjiyOmVbrJx7wnt1XFxL/O0IRDEjZuh1wj9/k XDKNKcCFf6s0MV90nOntLTsvZg== X-Google-Smtp-Source: ABdhPJw1gJ7AE1CMHUZrJYUzuwzN+S0bY+eJtfZmK8lUWtAOqAbz4U922OMRBMJKVYFiD2o3gkKaKQ== X-Received: by 2002:a5d:4fc4:: with SMTP id h4mr9037144wrw.129.1611150297963; Wed, 20 Jan 2021 05:44:57 -0800 (PST) Received: from localhost.localdomain ([2a02:2450:102f:d6a:93b3:1f80:ae7b:a5c6]) by smtp.gmail.com with ESMTPSA id t67sm4224075wmt.28.2021.01.20.05.44.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Jan 2021 05:44:57 -0800 (PST) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, robert.foss@linaro.org, todor.too@gmail.com, mchehab@kernel.org, robh+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, shawnguo@kernel.org, leoyang.li@nxp.com, geert+renesas@glider.be, vkoul@kernel.org, Anson.Huang@nxp.com, michael@walle.cc, agx@sigxcpu.org, max.oss.09@gmail.com, linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, AngeloGioacchino Del Regno , Andrey Konovalov , Laurent Pinchart Cc: Tomasz Figa , Azam Sadiq Pasha Kapatrala Syed , Sarvesh Sridutt , Jonathan Marek Subject: [PATCH v2 16/22] dt-bindings: media: camss: Add qcom, sdm845-camss binding Date: Wed, 20 Jan 2021 14:43:51 +0100 Message-Id: <20210120134357.1522254-16-robert.foss@linaro.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210120134357.1522254-1-robert.foss@linaro.org> References: <20210120134357.1522254-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Signed-off-by: Robert Foss --- Changes since v1: - Laurent: Reworked driver to use dtschema .../bindings/media/qcom,sdm845-camss.yaml | 394 ++++++++++++++++++ 1 file changed, 394 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml diff --git a/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml new file mode 100644 index 000000000000..40864a5ab2c5 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml @@ -0,0 +1,394 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/media/qcom,sdm845-camss.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm CAMSS ISP + +maintainers: + - Robert Foss + - Todor Tomov + +description: | + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms + +properties: + compatible: + const: qcom,sdm845-camss + + clocks: + description: + Input clocks for the hardware block. + minItems: 36 + maxItems: 36 + + clock-names: + description: + Names of input clocks for the hardware block. + items: + - const: camnoc_axi + - const: cpas_ahb + - const: cphy_rx_src + - const: csi0 + - const: csi0_src + - const: csi1 + - const: csi1_src + - const: csi2 + - const: csi2_src + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy0_timer_src + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy1_timer_src + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy2_timer_src + - const: csiphy3 + - const: csiphy3_timer + - const: csiphy3_timer_src + - const: gcc_camera_ahb + - const: gcc_camera_axi + - const: slow_ahb_src + - const: soc_ahb + - const: vfe0_axi + - const: vfe0 + - const: vfe0_cphy_rx + - const: vfe0_src + - const: vfe1_axi + - const: vfe1 + - const: vfe1_cphy_rx + - const: vfe1_src + - const: vfe_lite + - const: vfe_lite_cphy_rx + - const: vfe_lite_src + + interrupts: + description: + IRQs for the hardware block. + minItems: 10 + maxItems: 10 + + interrupt-names: + description: + Names of IRQs for the hardware block. + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: vfe0 + - const: vfe1 + - const: vfe_lite + + iommus: + maxItems: 4 + + power-domains: + maxItems: 3 + + ports: + description: + The CSI data input ports. + + type: object + + properties: + port@0: + type: object + description: Input node for receiving CSI data. + properties: + endpoint: + type: object + + properties: + clock-lanes: + description: |- + The physical clock lane index. + + data-lanes: + description: |- + An array of physical data lanes indexes. + Position of an entry determines the logical + lane number, while the value of an entry + indicates physical lane index. + + required: + - clock-lanes + - data-lanes + + required: + - endpoint + - reg + + port@1: + type: object + description: Input node for receiving CSI data. + properties: + endpoint: + type: object + + properties: + clock-lanes: + description: |- + The physical clock lane index. + + data-lanes: + description: |- + An array of physical data lanes indexes. + Position of an entry determines the logical + lane number, while the value of an entry + indicates physical lane index. + + required: + - clock-lanes + - data-lanes + + required: + - endpoint + - reg + + port@2: + type: object + description: Input node for receiving CSI data. + properties: + endpoint: + type: object + + properties: + clock-lanes: + description: |- + The physical clock lane index. + + data-lanes: + description: |- + An array of physical data lanes indexes. + Position of an entry determines the logical + lane number, while the value of an entry + indicates physical lane index. + + required: + - clock-lanes + - data-lanes + + required: + - endpoint + - reg + + port@3: + type: object + description: Input node for receiving CSI data. + properties: + endpoint: + type: object + + properties: + clock-lanes: + description: |- + The physical clock lane index. + + data-lanes: + description: |- + An array of physical data lanes indexes. + Position of an entry determines the logical + lane number, while the value of an entry + indicates physical lane index. + + required: + - clock-lanes + - data-lanes + + required: + - endpoint + - reg + + reg: + minItems: 10 + maxItems: 10 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: vfe0 + - const: vfe1 + - const: vfe_lite + + vdda-supply: + description: + Definition of the regulator used as analog power supply. + +required: + - clock-names + - clocks + - compatible + - interrupt-names + - interrupts + - iommus + - power-domains + - reg + - reg-names + - vdda-supply + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + camss: camss@a00000 { + compatible = "qcom,sdm845-camss"; + + clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY0_CLK>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY1_CLK>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY2_CLK>, + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY3_CLK>, + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_AXI_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_0_AXI_CLK>, + <&clock_camcc CAM_CC_IFE_0_CLK>, + <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_AXI_CLK>, + <&clock_camcc CAM_CC_IFE_1_CLK>, + <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>; + + clock-names = "camnoc_axi", + "cpas_ahb", + "cphy_rx_src", + "csi0", + "csi0_src", + "csi1", + "csi1_src", + "csi2", + "csi2_src", + "csiphy0", + "csiphy0_timer", + "csiphy0_timer_src", + "csiphy1", + "csiphy1_timer", + "csiphy1_timer_src", + "csiphy2", + "csiphy2_timer", + "csiphy2_timer_src", + "csiphy3", + "csiphy3_timer", + "csiphy3_timer_src", + "gcc_camera_ahb", + "gcc_camera_axi", + "slow_ahb_src", + "soc_ahb", + "vfe0_axi", + "vfe0", + "vfe0_cphy_rx", + "vfe0_src", + "vfe1_axi", + "vfe1", + "vfe1_cphy_rx", + "vfe1_src", + "vfe_lite", + "vfe_lite_cphy_rx", + "vfe_lite_src"; + + interrupts = , + , + , + , + , + , + , + , + , + ; + + interrupt-names = "csid0", + "csid1", + "csid2", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "vfe0", + "vfe1", + "vfe_lite"; + + iommus = <&apps_smmu 0x0808 0x0>, + <&apps_smmu 0x0810 0x8>, + <&apps_smmu 0x0c08 0x0>, + <&apps_smmu 0x0c10 0x8>; + + power-domains = <&clock_camcc IFE_0_GDSC>, + <&clock_camcc IFE_1_GDSC>, + <&clock_camcc TITAN_TOP_GDSC>; + + reg = <0 0xacb3000 0 0x1000>, + <0 0xacba000 0 0x1000>, + <0 0xacc8000 0 0x1000>, + <0 0xac65000 0 0x1000>, + <0 0xac66000 0 0x1000>, + <0 0xac67000 0 0x1000>, + <0 0xac68000 0 0x1000>, + <0 0xacaf000 0 0x4000>, + <0 0xacb6000 0 0x4000>, + <0 0xacc4000 0 0x4000>; + + reg-names = "csid0", + "csid1", + "csid2", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "vfe0", + "vfe1", + "vfe_lite"; + + vdda-supply = <®_2v8>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + +