From patchwork Wed Jan 20 13:43:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 367237 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CE85C433DB for ; Wed, 20 Jan 2021 21:09:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 32BE42343E for ; Wed, 20 Jan 2021 21:09:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726900AbhATUz2 (ORCPT ); Wed, 20 Jan 2021 15:55:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43622 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387762AbhATNsm (ORCPT ); Wed, 20 Jan 2021 08:48:42 -0500 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 70AEDC06138E for ; Wed, 20 Jan 2021 05:44:52 -0800 (PST) Received: by mail-wm1-x32a.google.com with SMTP id v184so2902618wma.1 for ; Wed, 20 Jan 2021 05:44:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LkZ99XoWXMbOO4g7PnTiwOPZK1LCMqlyf1JEPyZMdz8=; b=k470PfzQJ4mPG/ZHGsLXUKxxbiF/k4+J2RxbbrL3wGFDkUVswDBGPjTGRVQ7/qO2Ew TuWhfbHFoFn6N17z1FLaNSATwpB4fEojNMyB6Vcv0bt5KFtEg3kYaFQMQ8wdWxmfe6PE rXDcTT6mXa0ejjfmYTH29reqJe5Cpf22oG+yRStac+eMEnw3nxcwThA1dVzXfXvWB6vU PD505fPu5BQE56y0kje8rDXLNEG1DE6LaKfpE+J1nsPWYKedWj4OiB/aSyX+Ku3VjVwO durkk3kDmqy/RwH4awu5MOyEDwS1iFDcWQWZzWfMcMka9fg/esHQ5mvU0LAsuc3/DDwB 9A/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LkZ99XoWXMbOO4g7PnTiwOPZK1LCMqlyf1JEPyZMdz8=; b=BAExybfKY0JUj1kT9TvcKUP+ITNwSlHKPDBhQBFuJS/2tajpi6Dij+OHoEhbNFKlm7 5Qni2zjik3EiRFKT4R4sGEOqDaqCeNKR/qapV0ukrEw/CUYBY+gqXjPpk6H6IDgzaWtq Ez3t5umSufWmQLVxPpAXoVvDwAM76YmYR7FS0Tym+LZg0D5tts8czfe7x3N/oFao2lxp MJDVdFj8hxOJXsMct6TZCVP/JUYhOsmDjL59fIbdR0U8oxyfo4fvaijRyrsXGgznJoka FBio7xFdSoLViGNtAfzmRicrUAOSx09T9WHDpxnGsN7nNAVzGDIWgwcKC4emWo/NNagh jHyA== X-Gm-Message-State: AOAM5333wbQFXIeaDGQFUzK5CU7DZU51BoONJ/2veprofB3ooFNHxaB1 pUqfvYavAu1WHx6rR369YciXKA== X-Google-Smtp-Source: ABdhPJyHt28Lb05HKHpDnLz50i7lYj1GT2JcZ1hAwpc+Ij034gOCGS8CLTUoznBFwsFVnHGOcqvb3A== X-Received: by 2002:a05:600c:215:: with SMTP id 21mr4415492wmi.54.1611150291224; Wed, 20 Jan 2021 05:44:51 -0800 (PST) Received: from localhost.localdomain ([2a02:2450:102f:d6a:93b3:1f80:ae7b:a5c6]) by smtp.gmail.com with ESMTPSA id t67sm4224075wmt.28.2021.01.20.05.44.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Jan 2021 05:44:50 -0800 (PST) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, robert.foss@linaro.org, todor.too@gmail.com, mchehab@kernel.org, robh+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, shawnguo@kernel.org, leoyang.li@nxp.com, geert+renesas@glider.be, vkoul@kernel.org, Anson.Huang@nxp.com, michael@walle.cc, agx@sigxcpu.org, max.oss.09@gmail.com, linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, AngeloGioacchino Del Regno , Andrey Konovalov , Laurent Pinchart Cc: Tomasz Figa , Azam Sadiq Pasha Kapatrala Syed , Sarvesh Sridutt , Jonathan Marek Subject: [PATCH v2 13/22] dt-bindings: media: camss: Add qcom, msm8916-camss binding Date: Wed, 20 Jan 2021 14:43:48 +0100 Message-Id: <20210120134357.1522254-13-robert.foss@linaro.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210120134357.1522254-1-robert.foss@linaro.org> References: <20210120134357.1522254-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add bindings for qcom,msm8916-camss in order to support the camera subsystem on MSM8916. Signed-off-by: Robert Foss --- Changes since v1: - Laurent: Reworked driver to use dtschema .../bindings/media/qcom,msm8916-camss.yaml | 270 ++++++++++++++++++ 1 file changed, 270 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/qcom,msm8916-camss.yaml diff --git a/Documentation/devicetree/bindings/media/qcom,msm8916-camss.yaml b/Documentation/devicetree/bindings/media/qcom,msm8916-camss.yaml new file mode 100644 index 000000000000..f0b0c67d0f0c --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,msm8916-camss.yaml @@ -0,0 +1,270 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/media/qcom,msm8916-camss.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm CAMSS ISP + +maintainers: + - Robert Foss + - Todor Tomov + +description: | + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms + +properties: + compatible: + const: qcom,msm8916-camss + + clocks: + description: + Input clocks for the hardware block. + minItems: 19 + maxItems: 19 + + clock-names: + description: + Names of input clocks for the hardware block. + items: + - const: top_ahb + - const: ispif_ahb + - const: csiphy0_timer + - const: csiphy1_timer + - const: csi0_ahb + - const: csi0 + - const: csi0_phy + - const: csi0_pix + - const: csi0_rdi + - const: csi1_ahb + - const: csi1 + - const: csi1_phy + - const: csi1_pix + - const: csi1_rdi + - const: ahb + - const: vfe0 + - const: csi_vfe0 + - const: vfe_ahb + - const: vfe_axi + + interrupts: + description: + IRQs for the hardware block. + minItems: 6 + maxItems: 6 + + interrupt-names: + description: + Names of IRQs for the hardware block. + items: + - const: csiphy0 + - const: csiphy1 + - const: csid0 + - const: csid1 + - const: ispif + - const: vfe0 + + iommus: + maxItems: 1 + + power-domains: + maxItems: 1 + + ports: + description: + The CSI data input ports. + + type: object + + properties: + port@0: + type: object + description: Input node for receiving CSI data. + properties: + endpoint: + type: object + + properties: + clock-lanes: + description: |- + The physical clock lane index. The value + must always be <1> as the physical + clock lane is lane 1. + + data-lanes: + description: |- + An array of physical data lanes indexes. + Position of an entry determines the logical + lane number, while the value of an entry + indicates physical lane index. Lane swapping + is supported. Physical lane indexes: + 0, 2, 3, 4. + + required: + - clock-lanes + - data-lanes + + required: + - endpoint + - reg + + port@1: + type: object + description: Input node for receiving CSI data. + properties: + endpoint: + type: object + + properties: + clock-lanes: + description: |- + The physical clock lane index. The value + must always be <1> as the physical + clock lane is lane 1. + + data-lanes: + description: |- + An array of physical data lanes indexes. + Position of an entry determines the logical + lane number, while the value of an entry + indicates physical lane index. Lane swapping + is supported. Physical lane indexes: + 0, 2, 3, 4. + + required: + - clock-lanes + - data-lanes + + required: + - endpoint + - reg + + reg: + minItems: 9 + maxItems: 9 + + reg-names: + items: + - const: csiphy0 + - const: csiphy0_clk_mux + - const: csiphy1 + - const: csiphy1_clk_mux + - const: csid0 + - const: csid1 + - const: ispif + - const: csi_clk_mux + - const: vfe0 + + vdda-supply: + description: + Definition of the regulator used as analog power supply. + +required: + - clock-names + - clocks + - compatible + - interrupt-names + - interrupts + - iommus + - power-domains + - reg + - reg-names + - vdda-supply + +additionalProperties: false + +examples: + - | + #include + #include + + camss: camss@1b00000 { + compatible = "qcom,msm8916-camss"; + + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, + <&gcc GCC_CAMSS_CSI0_AHB_CLK>, + <&gcc GCC_CAMSS_CSI0_CLK>, + <&gcc GCC_CAMSS_CSI0PHY_CLK>, + <&gcc GCC_CAMSS_CSI0PIX_CLK>, + <&gcc GCC_CAMSS_CSI0RDI_CLK>, + <&gcc GCC_CAMSS_CSI1_AHB_CLK>, + <&gcc GCC_CAMSS_CSI1_CLK>, + <&gcc GCC_CAMSS_CSI1PHY_CLK>, + <&gcc GCC_CAMSS_CSI1PIX_CLK>, + <&gcc GCC_CAMSS_CSI1RDI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>, + <&gcc GCC_CAMSS_VFE0_CLK>, + <&gcc GCC_CAMSS_CSI_VFE0_CLK>, + <&gcc GCC_CAMSS_VFE_AHB_CLK>, + <&gcc GCC_CAMSS_VFE_AXI_CLK>; + + clock-names = "top_ahb", + "ispif_ahb", + "csiphy0_timer", + "csiphy1_timer", + "csi0_ahb", + "csi0", + "csi0_phy", + "csi0_pix", + "csi0_rdi", + "csi1_ahb", + "csi1", + "csi1_phy", + "csi1_pix", + "csi1_rdi", + "ahb", + "vfe0", + "csi_vfe0", + "vfe_ahb", + "vfe_axi"; + + interrupts = , + , + , + , + , + ; + + interrupt-names = "csiphy0", + "csiphy1", + "csid0", + "csid1", + "ispif", + "vfe0"; + + iommus = <&apps_iommu 3>; + + power-domains = <&gcc VFE_GDSC>; + + reg = <0x01b0ac00 0x200>, + <0x01b00030 0x4>, + <0x01b0b000 0x200>, + <0x01b00038 0x4>, + <0x01b08000 0x100>, + <0x01b08400 0x100>, + <0x01b0a000 0x500>, + <0x01b00020 0x10>, + <0x01b10000 0x1000>; + + reg-names = "csiphy0", + "csiphy0_clk_mux", + "csiphy1", + "csiphy1_clk_mux", + "csid0", + "csid1", + "ispif", + "csi_clk_mux", + "vfe0"; + + vdda-supply = <®_2v8>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + + };