From patchwork Wed Jan 20 11:21:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 368174 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BF80C433E9 for ; Wed, 20 Jan 2021 12:46:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 070A323382 for ; Wed, 20 Jan 2021 12:46:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388789AbhATMir (ORCPT ); Wed, 20 Jan 2021 07:38:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42542 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726672AbhATL3v (ORCPT ); Wed, 20 Jan 2021 06:29:51 -0500 Received: from mail-pg1-x52f.google.com (mail-pg1-x52f.google.com [IPv6:2607:f8b0:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C6EFC0613CF for ; Wed, 20 Jan 2021 03:22:18 -0800 (PST) Received: by mail-pg1-x52f.google.com with SMTP id v19so14956681pgj.12 for ; Wed, 20 Jan 2021 03:22:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=/G1XKKzyK0yZAshK+VzVtT1gmvcbma2qBK0WNAjoFJ0=; b=f9QxSmeFNcQFQsw7hS5QGeGaJxyqhXGEzo3QbjXqM2wj4ArTB1aEOtGsbeRw0Cfry7 Z/DoOVbz6XFlRGziXkPIHVr5CDG77H52tQekRcbd3EoBJSieaNdq4sOUvO8lrRzd6C3A D3KVS+yS1pwtyYt8XtxYOSAZdhSj7wr23Llrw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=/G1XKKzyK0yZAshK+VzVtT1gmvcbma2qBK0WNAjoFJ0=; b=VyXPQNZJCBSY9MazhntlOfFl2b+Q9Qp7sCN4P2ZD4FfI/6e1dqww5HbwK19HACc7JL T0CqoRAHhVGAThmxrRDj08yXBcdAwyb/P/dDgpFg+0qpx28QXjAFUBmb1UNqZlzW9FEn y6h48XzgK02eUcByhSfyBtqIGOHAahWE4uKCw1eRrT0uZAv3CtWuGRdRdWeL30uYKf4K E0U3T9f7kPyPKBlu/y3D06wRwuZHk0ln9yWGaQ6L2Cwm1OCLeyQ9vGuZfSobFyD9ws5V onqhN5iaXOsPeB1+vQhfKGot+90+EDb/wXAVIyHTfCu/LEpcJcUquedeXQbOPZb6n2PM C6/g== X-Gm-Message-State: AOAM531FRGlMXcGn2bvytBbJdVXwcEi6KzuI3uPY0IlfWtrWUd+trtuB S2hUcmxIe1lKbdIexiTarGBeMA== X-Google-Smtp-Source: ABdhPJwEhxynnzNsfdOIosnWD6hJRmKWPIAg2bWTvI3yFlUc2LWW0ORKLS7qvfBc2J2WLYigePeAKg== X-Received: by 2002:a65:4083:: with SMTP id t3mr8967439pgp.150.1611141737943; Wed, 20 Jan 2021 03:22:17 -0800 (PST) Received: from ub-XPS-13-9350.domain.name ([103.105.103.154]) by smtp.gmail.com with ESMTPSA id gk2sm2248341pjb.6.2021.01.20.03.22.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Jan 2021 03:22:17 -0800 (PST) From: Jagan Teki To: Rob Herring , Andrzej Hajda , Neil Armstrong , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Sam Ravnborg Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH 1/2] dt-bindings: display: bridge: Add documentation for SN65DSI84 Date: Wed, 20 Jan 2021 16:51:57 +0530 Message-Id: <20210120112158.62109-1-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org SN65DSI84 is a Single Channel DSI to Dual-link LVDS bridge from Texas Instruments. SN65DSI83, SN65DSI85 are variants of the same family of bridge controllers. Right now the bridge driver is supporting a single link, dual-link support requires to initiate I2C Channel B registers, so dt-bindings documented with single link LVDS. Signed-off-by: Jagan Teki --- .../bindings/display/bridge/ti,sn65dsi84.yaml | 127 ++++++++++++++++++ 1 file changed, 127 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi84.yaml diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi84.yaml b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi84.yaml new file mode 100644 index 000000000000..891382a76c1a --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi84.yaml @@ -0,0 +1,127 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/ti,sn65dsi84.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI SN65DSI84 MIPI DSI to LVDS bridge bindings + +maintainers: + - Jagan Teki + +description: | + The SN65DSI84 DSI to FlatLink bridge features a single channel MIPI D-PHY receiver + front-end configuration with 4 lanes per channel operating at 1 Gbps per lanes. + The bridge decodes MIPI DSI 18bpp RGB666 and 240bpp RG888 packets and converts + the formatted video data stream to a FlatLink compatible LVDS output operating + at pixel clocks operating from 25 MHx to 154 MHz, offering a Dual-Link LVDS, + Single-Link LVDS interface with four data lanes per link. + + https://www.ti.com/product/SN65DSI84 + +properties: + compatible: + const: ti,sn65dsi84 + + reg: + maxItems: 1 + description: i2c address of the bridge, 0x2c + + enable-gpios: + maxItems: 1 + description: GPIO specifier for bridge enable pin (active high). + + ports: + type: object + description: + A node containing input and output port nodes with endpoint definitions + as documented in + Documentation/devicetree/bindings/media/video-interfaces.txt + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + description: | + DSI Input. The remote endpoint phandle should be a + reference to a valid mipi_dsi_host device node. + + port@1: + type: object + description: | + Video port for LVDS output (panel or connector). + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - enable-gpios + - ports + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&bridge_in>; + data-lanes = <0 1>; + }; + }; + }; + }; + + i2c6 { + #address-cells = <1>; + #size-cells = <0>; + + bridge@2c { + compatible = "ti,sn65dsi84"; + reg = <0x2c>; + enable-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + bridge_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + bridge_out: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; + }; + };