From patchwork Fri Jan 15 19:30:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 363742 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp144779jap; Fri, 15 Jan 2021 11:31:58 -0800 (PST) X-Google-Smtp-Source: ABdhPJwRQwIfqZDXdstTGvak0240kXLcZXO/U0y3eUh51VALSmgIaHPCu47ljl97BvvwOEF+qTgn X-Received: by 2002:a05:6402:524a:: with SMTP id t10mr11011251edd.270.1610739118289; Fri, 15 Jan 2021 11:31:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610739118; cv=none; d=google.com; s=arc-20160816; b=pNsrxyFS/5HB1Hz887ohtZRNwjzBOLk8mZpy9ddGNF0PTq6zXtIySM5YlPAYZR8Xo9 kJoolAdfOh7CVv7+joeEvw+GOlrZyw4RnTLn+SVoWwmisouz5ce3vNFOBgacWVO8HeMF jdgIPRuyEsgSLkumqE9owCL/ySjsDAuyk6ijvAquXb/gedLnRqoKbdbMHO4612Y7svfU B+kj1sDtP46yLdcMVKhhLelkTJdSFsuhrh64bo1dN0C7S+VQGQOnFfvXOxaSVD8zukqS Os36JskGfW5Og6/ZmA4P5A2I2b/f/oxxWpXVOztpttcDpIdpL6hwpLAdDWG+ourDtKob Yvaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:message-id:date:subject:cc:to:from :dkim-signature; bh=ET3b8SQtXsK1u7lP8qHpr68KgMOdtU3PXzl1PkdKbyk=; b=gRn6jAFAa6mGFvgGZVL7rKpM0xAGjADR8O4hCztV93uLq2oHLJsuSuTzrnlwI0lxvz DWzlPKnD0+KcMdRSckPv1CsMEs9e5Uv5agrj6wOVzn4/7WNOY3OnWkzKWhjaHSGHlHQY xJvWZRsji+tRyssPDUKNfWHdbD+GYvin5Bk+cRnWyaNmZaLCX9U6yh2eW1IMGs5opLv1 mV8f4IMmpfW2FOqb+4RXdZSA2PcBELqdL6gKV+H6xQ6Wo4sRGBuZOsrEJi4Oo3d9R+nf jQG4QKPI5EjJ4FbjMuTQbgpULa3DgFAjAzY5H105rfgr49OF1+ztAqSXop/W/mP4OVa1 xh0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=tePT5emK; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id d3si4858373edj.258.2021.01.15.11.31.58; Fri, 15 Jan 2021 11:31:58 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=tePT5emK; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388198AbhAOTbR (ORCPT + 6 others); Fri, 15 Jan 2021 14:31:17 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:38840 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729990AbhAOTbR (ORCPT ); Fri, 15 Jan 2021 14:31:17 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 10FJUUSj068473; Fri, 15 Jan 2021 13:30:30 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1610739030; bh=ET3b8SQtXsK1u7lP8qHpr68KgMOdtU3PXzl1PkdKbyk=; h=From:To:CC:Subject:Date; b=tePT5emK2GXilA8mvAq8RtwVucQpuxMy4rhnRSgUmmVkZIGeJ8jkqbgjpS5Jc7VU2 taSw63g3M4XfMUdJlj+lZ4arOf0DOhvH4xo2bKEPY2X5zT50bCcQBg6r2zC+gEcWU8 NtSNcsOI6+yjt99lACnWyLpkd1Wa8JLT4gvVuJG8= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 10FJUUKX097645 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 15 Jan 2021 13:30:30 -0600 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 15 Jan 2021 13:30:30 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 15 Jan 2021 13:30:30 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 10FJUTa6061349; Fri, 15 Jan 2021 13:30:29 -0600 From: Grygorii Strashko To: Nishanth Menon , , , Faiz Abbas CC: , Rob Herring , Vignesh Raghavendra , Ulf Hansson , Grygorii Strashko Subject: [PATCH] arm64: dts: ti: k3: mmc: fix dtbs_check warnings Date: Fri, 15 Jan 2021 21:30:16 +0200 Message-ID: <20210115193016.5581-1-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Now the dtbs_check produces below warnings sdhci@4f80000: clock-names:0: 'clk_ahb' was expected sdhci@4f80000: clock-names:1: 'clk_xin' was expected $nodename:0: 'sdhci@4f80000' does not match '^mmc(@.*)?$' Fix above warnings by updating mmc DT definitions to follow sdhci-am654.yaml bindings: - rename sdhci dt nodes to 'mmc@' - swap clk_xin/clk_ahb clocks, the clk_ahb clock expected to be defined first Signed-off-by: Grygorii Strashko --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 4 ++-- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 8 ++++---- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 18 +++++++++--------- 3 files changed, 15 insertions(+), 15 deletions(-) -- 2.17.1 Reviewed-by: Aswath Govindraju Reviewed-by: Suman Anna diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 12591a854020..ceb579fb427d 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -256,7 +256,7 @@ #size-cells = <0>; }; - sdhci0: sdhci@4f80000 { + sdhci0: mmc@4f80000 { compatible = "ti,am654-sdhci-5.1"; reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>; power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; @@ -280,7 +280,7 @@ dma-coherent; }; - sdhci1: sdhci@4fa0000 { + sdhci1: mmc@4fa0000 { compatible = "ti,am654-sdhci-5.1"; reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>; power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 4e39f0325c03..3f23b913b498 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -506,8 +506,8 @@ reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; interrupts = ; power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&k3_clks 91 3>, <&k3_clks 91 0>; + clock-names = "clk_ahb", "clk_xin"; + clocks = <&k3_clks 91 0>, <&k3_clks 91 3>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; ti,otap-del-sel-ddr52 = <0x6>; @@ -525,8 +525,8 @@ reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; interrupts = ; power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&k3_clks 92 2>, <&k3_clks 92 1>; + clock-names = "clk_ahb", "clk_xin"; + clocks = <&k3_clks 92 1>, <&k3_clks 92 2>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 2d526ea44a85..8c84dafb7125 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1032,13 +1032,13 @@ clock-names = "gpio"; }; - main_sdhci0: sdhci@4f80000 { + main_sdhci0: mmc@4f80000 { compatible = "ti,j721e-sdhci-8bit"; reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; interrupts = ; power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&k3_clks 91 1>, <&k3_clks 91 0>; + clock-names = "clk_ahb", "clk_xin"; + clocks = <&k3_clks 91 0>, <&k3_clks 91 1>; assigned-clocks = <&k3_clks 91 1>; assigned-clock-parents = <&k3_clks 91 2>; bus-width = <8>; @@ -1054,13 +1054,13 @@ dma-coherent; }; - main_sdhci1: sdhci@4fb0000 { + main_sdhci1: mmc@4fb0000 { compatible = "ti,j721e-sdhci-4bit"; reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; interrupts = ; power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&k3_clks 92 0>, <&k3_clks 92 5>; + clock-names = "clk_ahb", "clk_xin"; + clocks = <&k3_clks 92 5>, <&k3_clks 92 0>; assigned-clocks = <&k3_clks 92 0>; assigned-clock-parents = <&k3_clks 92 1>; ti,otap-del-sel-legacy = <0x0>; @@ -1074,13 +1074,13 @@ dma-coherent; }; - main_sdhci2: sdhci@4f98000 { + main_sdhci2: mmc@4f98000 { compatible = "ti,j721e-sdhci-4bit"; reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; interrupts = ; power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&k3_clks 93 0>, <&k3_clks 93 5>; + clock-names = "clk_ahb", "clk_xin"; + clocks = <&k3_clks 93 5>, <&k3_clks 93 0>; assigned-clocks = <&k3_clks 93 0>; assigned-clock-parents = <&k3_clks 93 1>; ti,otap-del-sel-legacy = <0x0>;