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Mon, 4 Jan 2021 09:16:35 +0000 From: "Alice Guo (OSS)" To: robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, krzk@kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-imx@nxp.com Subject: [PATCH v10 3/4] arm64: dts: imx8m: add NVMEM provider and consumer to read soc unique ID Date: Mon, 4 Jan 2021 17:15:43 +0800 Message-Id: <20210104091544.13972-3-alice.guo@oss.nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210104091544.13972-1-alice.guo@oss.nxp.com> References: <20210104091544.13972-1-alice.guo@oss.nxp.com> X-Originating-IP: [119.31.174.71] X-ClientProxiedBy: AM0PR10CA0055.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:20b:150::35) To AM6PR04MB6053.eurprd04.prod.outlook.com (2603:10a6:20b:b9::10) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from nxf55104-OptiPlex-7060.ap.freescale.net (119.31.174.71) by AM0PR10CA0055.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:20b:150::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3721.20 via Frontend Transport; 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Reviewed-by: Krzysztof Kozlowski Signed-off-by: Alice Guo --- Changes for v10: - none Changes for v9: - re-add Reviewed-by because it was lost in v8 Changes for v8: - lost Reviewed-by carelessly Changes for v7: - add Reviewed-by Changes for v6: - leave only the changelog under '---' Changes for v5: - change underscore of device node to hyphen Changes for v4: - delete "stuff" in subject and commit message - add detailed description Changes for v3: - convert register addresses and sizes to hex Changes for v2: - remove the subject prefix "LF-2571-3" arch/arm64/boot/dts/freescale/imx8mm.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/imx8mn.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/imx8mq.dtsi | 6 ++++++ 4 files changed, 24 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index d457ce815e68..9bee6f1889a4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -261,6 +261,8 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; + nvmem-cells = <&imx8mm_uid>; + nvmem-cell-names = "soc_unique_id"; aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; @@ -518,6 +520,10 @@ #address-cells = <1>; #size-cells = <1>; + imx8mm_uid: unique-id@410 { + reg = <0x4 0x8>; + }; + cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index db50e6e01ac5..b344fdc16534 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -245,6 +245,8 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; + nvmem-cells = <&imx8mn_uid>; + nvmem-cell-names = "soc_unique_id"; aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; @@ -531,6 +533,10 @@ #address-cells = <1>; #size-cells = <1>; + imx8mn_uid: unique-id@410 { + reg = <0x4 0x8>; + }; + cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index ec6ac523ecfc..9401e92f1c84 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -222,6 +222,8 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; + nvmem-cells = <&imx8mp_uid>; + nvmem-cell-names = "soc_unique_id"; aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; @@ -328,6 +330,10 @@ #address-cells = <1>; #size-cells = <1>; + imx8mp_uid: unique-id@420 { + reg = <0x8 0x8>; + }; + cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 9b6d9307e5d7..a2a885f1a07a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -291,6 +291,8 @@ #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; + nvmem-cells = <&imx8mq_uid>; + nvmem-cell-names = "soc_unique_id"; bus@30000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; @@ -555,6 +557,10 @@ #address-cells = <1>; #size-cells = <1>; + imx8mq_uid: soc-uid@410 { + reg = <0x4 0x8>; + }; + cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; };