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[109.252.192.57]) by smtp.gmail.com with ESMTPSA id u5sm655596lff.78.2020.12.17.10.07.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Dec 2020 10:07:26 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Mark Brown , Liam Girdwood , Ulf Hansson , Mauro Carvalho Chehab , Rob Herring , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski , "Rafael J. Wysocki" , Kevin Hilman , Peter De Schrijver , Viresh Kumar , Stephen Boyd , Michael Turquette Cc: devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 06/48] dt-bindings: clock: tegra: Document clocks sub-node Date: Thu, 17 Dec 2020 21:05:56 +0300 Message-Id: <20201217180638.22748-7-digetx@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201217180638.22748-1-digetx@gmail.com> References: <20201217180638.22748-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document "clocks" sub-node which describes Tegra SoC clocks that require a higher voltage of the core power domain in order to operate properly on a higher rates. Signed-off-by: Dmitry Osipenko --- .../bindings/clock/nvidia,tegra20-car.txt | 26 +++++++++++++++++++ .../bindings/clock/nvidia,tegra30-car.txt | 26 +++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt index 6c5901b503d0..353354477785 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt @@ -19,6 +19,16 @@ Required properties : In clock consumers, this cell represents the bit number in the CAR's array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. +Optional child sub-node "clocks" should contain nodes matching the clocks +on the Tegra SoC. Refer to Tegra TRM for mode details on the clock nodes. + +Required properties : +- compatible : Should be "nvidia,tegra20-clock". +- operating-points-v2: See ../bindings/opp/opp.txt for details. +- clocks : Should contain clock which corresponds to the node. +- power-domains: Phandle to a power domain node as described by generic + PM domain bindings. + Example SoC include file: / { @@ -27,6 +37,22 @@ Example SoC include file: reg = <0x60006000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + + clocks { + hdmi { + compatible = "nvidia,tegra20-clock"; + operating-points-v2 = <&hdmi_opp_table>; + clocks = <&tegra_car TEGRA20_CLK_HDMI>; + power-domains = <&domain>; + }; + + pll_m { + compatible = "nvidia,tegra20-clock"; + operating-points-v2 = <&pll_m_opp_table>; + clocks = <&tegra_car TEGRA20_CLK_PLL_M>; + power-domains = <&domain>; + }; + }; }; usb@c5004000 { diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt index 63618cde12df..bc7bbdaa9d3f 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt @@ -19,6 +19,16 @@ Required properties : In clock consumers, this cell represents the bit number in the CAR's array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. +Optional child sub-node "clocks" should contain nodes matching the clocks +on the Tegra SoC. Refer to Tegra TRM for mode details on the clock nodes. + +Required properties : +- compatible : Should be "nvidia,tegra30-clock". +- operating-points-v2: See ../bindings/opp/opp.txt for details. +- clocks : Should contain clock which corresponds to the node. +- power-domains: Phandle to a power domain node as described by generic + PM domain bindings. + Example SoC include file: / { @@ -31,6 +41,22 @@ Example SoC include file: usb@c5004000 { clocks = <&tegra_car TEGRA30_CLK_USB2>; + + clocks { + hdmi { + compatible = "nvidia,tegra30-clock"; + operating-points-v2 = <&hdmi_opp_table>; + clocks = <&tegra_car TEGRA30_CLK_HDMI>; + power-domains = <&domain>; + }; + + pll_m { + compatible = "nvidia,tegra30-clock"; + operating-points-v2 = <&pll_m_opp_table>; + clocks = <&tegra_car TEGRA30_CLK_PLL_M>; + power-domains = <&domain>; + }; + }; }; };