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[23.128.96.18]) by mx.google.com with ESMTP id m10si2608734eja.453.2020.12.10.05.10.42; Thu, 10 Dec 2020 05:10:42 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=X63AumFz; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389074AbgLJNKU (ORCPT + 6 others); Thu, 10 Dec 2020 08:10:20 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:39754 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388999AbgLJNKI (ORCPT ); Thu, 10 Dec 2020 08:10:08 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0BAD8TQD060576; Thu, 10 Dec 2020 07:08:29 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1607605709; bh=v8DeDg+aSnj9XDWh6SjoEmvU220d2QLKrD8S48HIXT4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=X63AumFzKo7DEDenEv1hNc68+rT9i7yeNC5wA2fYE6d9kSfbpMiz0bB9ilIG/I/0t jkHni3dCtn615zzulRMlBKuvcHTuQQBQZjkSAwbGr2d5K9Xc/VELHfji4F8DhXjzU8 vdDL252m/zRndxQ93JkbeptQG8fYgUMV/0UmDKfM= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0BAD8TWP118676 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 10 Dec 2020 07:08:29 -0600 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 10 Dec 2020 07:08:28 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 10 Dec 2020 07:08:28 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BAD7ral098988; Thu, 10 Dec 2020 07:08:26 -0600 From: Kishon Vijay Abraham I To: Tero Kristo , Nishanth Menon , Rob Herring , Kishon Vijay Abraham I CC: , , Subject: [PATCH v2 6/6] arm64: dts: ti: k3-j7200-common-proc-board: Enable PCIe Date: Thu, 10 Dec 2020 18:37:47 +0530 Message-ID: <20201210130747.25436-7-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201210130747.25436-1-kishon@ti.com> References: <20201210130747.25436-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org x2 lane PCIe slot in the common processor board is enabled and connected to j7200 SOM. Add PCIe DT node in common processor board to reflect the same. Signed-off-by: Kishon Vijay Abraham I --- .../boot/dts/ti/k3-j7200-common-proc-board.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index def98f563336..4a7182abccf5 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "k3-j7200-som-p0.dtsi" +#include #include #include #include @@ -241,3 +242,17 @@ resets = <&serdes_wiz0 3>; }; }; + +&pcie1_rc { + reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; +}; + +&pcie1_ep { + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; + status = "disabled"; +};