From patchwork Tue Dec 8 12:46:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 339736 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3663438jai; Tue, 8 Dec 2020 04:52:53 -0800 (PST) X-Google-Smtp-Source: ABdhPJzzanoxNcRWGQFPo3zMN8S8rfMKrwF0qar0SodCkRNrRdoo+efztcUGrCI8cePbnYZoAEUi X-Received: by 2002:a17:906:578e:: with SMTP id k14mr17836068ejq.90.1607431973821; Tue, 08 Dec 2020 04:52:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607431973; cv=none; d=google.com; s=arc-20160816; b=tsuaFRV8lzmraYWMsZt5TLKHiB2eK+wptv1ZEiKvxrXdPl8DFkQIvWQpL4cGgpgqeQ PyH+SGVWm5V5rWmNsAE8/nke32IK3kD6/6mVjvOgRZ7kGoDL6hiqjWWhV+7zXTahqDrZ P3l0rPJvLwiyv2pSk3ZEVhI+gqMad5v1ykAJucQN68LqQQ9D7ZuZMJB4Ehh7L9mWdhkF IaFgl+vPR7R2EORi1ScSO1jLszCgF7gV4osGOw9sr/389bHLfkqbS5sQZML8h5JsiUfO 2yoIdCV8C0ETC1BrQSRty8K2d5RmoCAAghpZQemhSl56jCHjHih7QUI+GXiZCZJZ2Rij w4KQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=epkydfdfqreN/nkFvLIQRqu/sHuaiglc7nVJIZ4MZb4=; b=PaJBqs2RC28KilA9QMOyhOkHu0S5o8iFD6KW3FYAfQCZkt+j+r3Ltt3iEuGMv07xIO +UrbMoPNHyEUv0RQmQm6YJdMqdSazdPMf7Vx+AM49G0eCemJBw3EsEg+cSm9DPvHWxrG EvRclT2LEED3amLwfS24PW4ObGOQIaWIVRzXkOhzecJdR4WMuJuvSd97c8XEdTFY2oCb HyP5mpus0F18etIIch4GVTzrAI7W3L4Xl77amFWZfO2r/GTQrE1B5usxBpeONOnFfLWJ d5kb6DTsBLLiWdNkfUjMJMnFmuXs8x5Txnf+dwNJ2XdviYtrsUMimyuv58hLOxjsArtT PyLQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id m11si10059482edr.583.2020.12.08.04.52.53; Tue, 08 Dec 2020 04:52:53 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726931AbgLHMv1 (ORCPT + 6 others); Tue, 8 Dec 2020 07:51:27 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:9132 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728653AbgLHMv1 (ORCPT ); Tue, 8 Dec 2020 07:51:27 -0500 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4Cr0QD0rMZz15YnB; Tue, 8 Dec 2020 20:50:12 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.9) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.487.0; Tue, 8 Dec 2020 20:50:34 +0800 From: Zhen Lei To: Philipp Zabel , Wei Xu , "Rob Herring" , linux-arm-kernel , devicetree , linux-kernel CC: Zhen Lei , Zhangfei Gao , Chen Feng , "Manivannan Sadhasivam" Subject: [PATCH v3 2/4] arm64: dts: correct vendor prefix hisi to hisilicon Date: Tue, 8 Dec 2020 20:46:39 +0800 Message-ID: <20201208124641.1787-3-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20201208124641.1787-1-thunder.leizhen@huawei.com> References: <20201208124641.1787-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.9] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The vendor prefix of "Hisilicon Limited" is "hisilicon", it is clearly stated in "vendor-prefixes.yaml". Fixes: 35ca8168133c ("arm64: dts: Add dts files for Hisilicon Hi3660 SoC") Fixes: dd8c7b78c11b ("arm64: dts: Add devicetree for Hisilicon Hi3670 SoC") Signed-off-by: Zhen Lei Cc: Chen Feng Cc: Manivannan Sadhasivam --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 4 ++-- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) -- 1.8.3 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 49c19c6879f95ce..bfb1375426d2b58 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -345,7 +345,7 @@ crg_rst: crg_rst_controller { compatible = "hisilicon,hi3660-reset"; #reset-cells = <2>; - hisi,rst-syscon = <&crg_ctrl>; + hisilicon,rst-syscon = <&crg_ctrl>; }; @@ -376,7 +376,7 @@ iomcu_rst: reset { compatible = "hisilicon,hi3660-reset"; - hisi,rst-syscon = <&iomcu>; + hisilicon,rst-syscon = <&iomcu>; #reset-cells = <2>; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 85b0dfb35d6d396..5c5a5dc964ea848 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -155,7 +155,7 @@ compatible = "hisilicon,hi3670-reset", "hisilicon,hi3660-reset"; #reset-cells = <2>; - hisi,rst-syscon = <&crg_ctrl>; + hisilicon,rst-syscon = <&crg_ctrl>; }; pctrl: pctrl@e8a09000 {