From patchwork Tue Dec 8 09:04:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 339705 Delivered-To: patch@linaro.org Received: by 2002:a17:906:4755:0:0:0:0 with SMTP id j21csp3617643ejs; Tue, 8 Dec 2020 01:05:41 -0800 (PST) X-Google-Smtp-Source: ABdhPJyaPei0zVOcfxpNB+T3X6BV7tTK0LImjYGJUWDoTXodO+T9wyiWp+RGeDyXtlY3Ur/idxMQ X-Received: by 2002:a17:906:ae55:: with SMTP id lf21mr22359450ejb.101.1607418341602; Tue, 08 Dec 2020 01:05:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607418341; cv=none; d=google.com; s=arc-20160816; b=M//f234N5OoWWR5wIkMuUqa6Vhdm1jGw9q3EFdvAxoSG1w9Buzaqfaf9szT0wqUyEA 9GvzmXumCvy9lFIdWpzWAc7p/YUAG1KQpe6EDG7BsWj7lx00EZfVx/E28dR6aXRMiEkp cLz1YahGnPpzGco3KUHyZblNrQqxIreHooXcqfrt1WQX1jjZUlbk0ArBsjJGe34nBjRj rqQ0TJc701rvf9eBVBGpTH/nt00g0Sz7/wGXQP3NbhA1bQ1HX32yDHVK/IgwpjvK7IGf TqYIuYU7RyQbwKMJuT23B4rtrqVf3asEqp8SOQXsQUyY7GoNRPXXgvD81oQYHutt/GTr Z3eg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=KNHtOiRh0Y2sF99V/npiBOhsYhLCYE7wypMinM3S5uw=; b=ZG3mGxN3yl/oHP7RL73ScfZlped/Gi5b3i+/GNpSLwgA9QRjk0c4jMwnZwwG5UicE4 BxPKZ0qIofg2FfOaPkO8xSqvaxoY5SyhxnOm3Ohzp2YpZ7BRWJmEsR6w1KMDPSR2WS1I vZw5WKq21LR6rV8OErzWA6ochkXqGSIU9ICqxO9TR9aGg8160HcHl7NnqLzFRXWmgeMF 4Hh0oVovx5KWWTikZPzprkKlBZDQp5Q0J7cU2NKcH2HxnaTL0C1u9Ycc5klQAeX4HQ39 Xoi6XImqFYf0pET8qPpznxtRZ8taFQKtNiC31Bk7uGg84cvxd6I6zZpu9Tr/0aEwT/9I 7FmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=YtGSHgPQ; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id h18si5193516eds.65.2020.12.08.01.05.41; Tue, 08 Dec 2020 01:05:41 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=YtGSHgPQ; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728184AbgLHJFA (ORCPT + 6 others); Tue, 8 Dec 2020 04:05:00 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:51726 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728189AbgLHJFA (ORCPT ); Tue, 8 Dec 2020 04:05:00 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0B8945rK130313; Tue, 8 Dec 2020 03:04:05 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1607418245; bh=KNHtOiRh0Y2sF99V/npiBOhsYhLCYE7wypMinM3S5uw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=YtGSHgPQE4LbTi+HtLsL5B2DkVplw8Mudd/mttWwVvxK0XYCb0xbD0H+TEHh2rcT+ 8ays2SIBqTa72Tcy0LE31Q0pxRM08Cfv4J8daSdS3+C0PuhBwhZ/btKsd1/Ep/QZ59 tHxD1nTJcl8RIug5hOLQURm1Pve0IeLPnZnmK8qA= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0B8945mg095309 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Dec 2020 03:04:05 -0600 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 8 Dec 2020 03:04:05 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 8 Dec 2020 03:04:05 -0600 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0B893dcB120112; Tue, 8 Dec 2020 03:04:02 -0600 From: Peter Ujfalusi To: , , , CC: , , , , , , , Subject: [PATCH v3 06/20] dmaengine: ti: k3-udma-glue: Configure the dma_dev for rings Date: Tue, 8 Dec 2020 11:04:26 +0200 Message-ID: <20201208090440.31792-7-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201208090440.31792-1-peter.ujfalusi@ti.com> References: <20201208090440.31792-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Rings in RING mode should be using the DMA device for DMA API as in this mode the ringacc will not access the ring memory in any ways, but the DMA is. Fix up the ring configuration and set the dma_dev unconditionally and let the ringacc driver to select the correct device to use for DMA API. Signed-off-by: Peter Ujfalusi --- drivers/dma/ti/k3-udma-glue.c | 8 ++++++++ 1 file changed, 8 insertions(+) -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki Reviewed-by: Grygorii Strashko diff --git a/drivers/dma/ti/k3-udma-glue.c b/drivers/dma/ti/k3-udma-glue.c index 8a8988be4175..e6ebcd98c02a 100644 --- a/drivers/dma/ti/k3-udma-glue.c +++ b/drivers/dma/ti/k3-udma-glue.c @@ -276,6 +276,10 @@ struct k3_udma_glue_tx_channel *k3_udma_glue_request_tx_chn(struct device *dev, goto err; } + /* Set the dma_dev for the rings to be configured */ + cfg->tx_cfg.dma_dev = k3_udma_glue_tx_get_dma_device(tx_chn); + cfg->txcq_cfg.dma_dev = cfg->tx_cfg.dma_dev; + ret = k3_ringacc_ring_cfg(tx_chn->ringtx, &cfg->tx_cfg); if (ret) { dev_err(dev, "Failed to cfg ringtx %d\n", ret); @@ -591,6 +595,10 @@ static int k3_udma_glue_cfg_rx_flow(struct k3_udma_glue_rx_channel *rx_chn, goto err_rflow_put; } + /* Set the dma_dev for the rings to be configured */ + flow_cfg->rx_cfg.dma_dev = k3_udma_glue_rx_get_dma_device(rx_chn); + flow_cfg->rxfdq_cfg.dma_dev = flow_cfg->rx_cfg.dma_dev; + ret = k3_ringacc_ring_cfg(flow->ringrx, &flow_cfg->rx_cfg); if (ret) { dev_err(dev, "Failed to cfg ringrx %d\n", ret);