From patchwork Tue Dec 8 06:46:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 339697 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3443011jai; Mon, 7 Dec 2020 22:48:51 -0800 (PST) X-Google-Smtp-Source: ABdhPJw+dAZ023Tdq+GayT12ZOGACbwJGu3wY9SSAkjwiuCYxvm2of3o9MmsSUrkngoIqZzN1OEQ X-Received: by 2002:aa7:c403:: with SMTP id j3mr23046558edq.217.1607410130948; Mon, 07 Dec 2020 22:48:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607410130; cv=none; d=google.com; s=arc-20160816; b=yXB2trkjIwE56+y2peSQ1SXsiVeAzOhXxI8zhej3FDDAE3ogcYTw9xriAQLwGa03a3 H+kkPoYlgkQHDRn4uxKRrXY1eakJZLHQMCiFv8QJ6SlsWCc1AP7uuGS/TAB+wEiHzKY2 Iiohw1UNhHMQd/31E7BQA1qcg3QSDQzd3GXcDN7Eb7mFu7mCqAHHEXMea/F5B/tOyCmo e9Eqn2nYRPI/Ajkviz+I2NB+seW2b7BvQr8LQC3zX2qAQ2NpfHv619+9zHrui+8Y4nKs +uCVQuQJCmKZmr9V0ecG4zSMUwGjpNTpGwLI2DTIJjFENWcfI354gURxgsok810S6CrF tb/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=CDb6UVnKlTNVHQOnpFR6mIiA+TcK2A5WjYPKF4lspY8=; b=ajuZtG42y9bIqg+a49+YZaHAIlEjxzOfM2MbXrXFGm+AvMxwh6L0rKBwrKkeZKbxQd wy8U4z6DY3MrZ/UogNgJR8gENeAml0yHU9laXOe5g9X/g9sy/3Nf9TE08aSbsKv65fXG MFQNgqnBtgiVJ4lR7q3WHgfPIcclRG5Vkd8guT7pUMJgjWHdO3ylNdqJ1httLdYWz5Mk gC+d0sDFn2A57fB4KIfMkIP9QpVcvu9SSX12h2f3S2Xxwv2KUeSYnQaCeAV1asmePa2K lw0QzmDPkQN+TxMvlyslvXueAUrs7uMNzUxIBXemNQCGHqBjv80MenINFLDmepv7gGBZ WpZA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id a7si9583068edy.150.2020.12.07.22.48.50; Mon, 07 Dec 2020 22:48:50 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725910AbgLHGsE (ORCPT + 6 others); Tue, 8 Dec 2020 01:48:04 -0500 Received: from mail.kernel.org ([198.145.29.99]:57496 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726255AbgLHGsE (ORCPT ); Tue, 8 Dec 2020 01:48:04 -0500 From: Vinod Koul Authentication-Results: mail.kernel.org; dkim=permerror (bad message/signature format) To: Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , Andy Gross , Michael Turquette , Rob Herring , Taniya Das , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/5] clk: qcom: rpmh: add support for SM8350 rpmh clocks Date: Tue, 8 Dec 2020 12:16:59 +0530 Message-Id: <20201208064702.3654324-3-vkoul@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201208064702.3654324-1-vkoul@kernel.org> References: <20201208064702.3654324-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds the RPMH clocks present in SM8350 SoC Reviewed-by: Bjorn Andersson Signed-off-by: Vinod Koul --- drivers/clk/qcom/clk-rpmh.c | 34 +++++++++++++++++++++++++++ include/dt-bindings/clock/qcom,rpmh.h | 8 +++++++ 2 files changed, 42 insertions(+) -- 2.26.2 diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index e2c669b08aff..64cab4403a17 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -432,6 +432,39 @@ static const struct clk_rpmh_desc clk_rpmh_sm8250 = { .num_clks = ARRAY_SIZE(sm8250_rpmh_clocks), }; +DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, div_clk1_ao, "divclka1", 2); +DEFINE_CLK_RPMH_VRM(sm8350, rf_clk4, rf_clk4_ao, "rfclka4", 1); +DEFINE_CLK_RPMH_VRM(sm8350, rf_clk5, rf_clk5_ao, "rfclka5", 1); +DEFINE_CLK_RPMH_BCM(sm8350, pka, "PKA0"); +DEFINE_CLK_RPMH_BCM(sm8350, hwkm, "HK0"); + +static struct clk_hw *sm8350_rpmh_clocks[] = { + [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, + [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, + [RPMH_DIV_CLK1] = &sm8350_div_clk1.hw, + [RPMH_DIV_CLK1_A] = &sm8350_div_clk1_ao.hw, + [RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1.hw, + [RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_ao.hw, + [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, + [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, + [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, + [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, + [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw, + [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw, + [RPMH_RF_CLK4] = &sm8350_rf_clk4.hw, + [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw, + [RPMH_RF_CLK5] = &sm8350_rf_clk5.hw, + [RPMH_RF_CLK5_A] = &sm8350_rf_clk5_ao.hw, + [RPMH_IPA_CLK] = &sdm845_ipa.hw, + [RPMH_PKA_CLK] = &sm8350_pka.hw, + [RPMH_HWKM_CLK] = &sm8350_hwkm.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_sm8350 = { + .clks = sm8350_rpmh_clocks, + .num_clks = ARRAY_SIZE(sm8350_rpmh_clocks), +}; + static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, void *data) { @@ -519,6 +552,7 @@ static const struct of_device_id clk_rpmh_match_table[] = { { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845}, { .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150}, { .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250}, + { .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350}, { } }; MODULE_DEVICE_TABLE(of, clk_rpmh_match_table); diff --git a/include/dt-bindings/clock/qcom,rpmh.h b/include/dt-bindings/clock/qcom,rpmh.h index 2e6c54e65455..6dbe5d398bf0 100644 --- a/include/dt-bindings/clock/qcom,rpmh.h +++ b/include/dt-bindings/clock/qcom,rpmh.h @@ -21,5 +21,13 @@ #define RPMH_IPA_CLK 12 #define RPMH_LN_BB_CLK1 13 #define RPMH_LN_BB_CLK1_A 14 +#define RPMH_DIV_CLK1 15 +#define RPMH_DIV_CLK1_A 16 +#define RPMH_RF_CLK4 17 +#define RPMH_RF_CLK4_A 18 +#define RPMH_RF_CLK5 19 +#define RPMH_RF_CLK5_A 20 +#define RPMH_PKA_CLK 21 +#define RPMH_HWKM_CLK 22 #endif