From patchwork Thu Dec 3 12:02:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 336932 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp232747ilb; Thu, 3 Dec 2020 04:04:09 -0800 (PST) X-Google-Smtp-Source: ABdhPJyL2jNyyMKRq0Xa8sOZLziAvDGl6pawGEEfRLU/y+pMyIAgY7YRQwT9rlbS2PA92QVTG3Vb X-Received: by 2002:a17:906:cecd:: with SMTP id si13mr75789ejb.441.1606997049451; Thu, 03 Dec 2020 04:04:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606997049; cv=none; d=google.com; s=arc-20160816; b=s+Xf1eC6aZlF8UFJ8AkeeWNmgDELzakvSM2mKXt1EgheF2marzkD9L1chwZnepEQT9 qs7x/QBjgPSMiIYoekanrDlLkddCOdEI/St6ETkAL7NkIpffNyBYUsz57f+UNwCbwMoH JuJ/W6MZ/Q/41v8KLG/J5z/PUtuSt6LA5W0+CxJoR9Rh5k2zLgvmIZ+3mYVtN68NjHHr aGp+oflwR3w2GPbfutXF3PBnvR67ZXAbUyuibClbiVOCYOXaGtnlZReFOcKtORJneMSA BXln1JcO2JvD07gPxbAOC2HjeTX/ZZ5Eo1nehmcHnpIQurulunGRgQuBh88MdcdvzOFB M6AA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=epkydfdfqreN/nkFvLIQRqu/sHuaiglc7nVJIZ4MZb4=; b=m11USa4NFDJr07yCSTlHl60v/4v7TQT3td4M2JdidU9hCrgW9UUUAQ5rmYYwBp7Nvo dBKsJTGq50xlUd1MNwIJgPabjmw1L9U75cK9JqaHu7kqIbD1t34Tpfeonqv4j534/HcB LKWUfryqIkQ7hwnlsMnJskE/AlAPPEexre7YCWSbOMYtv4jtz3bSat2KnbRKx33zXdrM NqftRcpKjXPrrc8MKjR8Ocm32U+7BozTg+1py39Y4ir/BsIy//wM6GflHWRFPwf93l/d 34EZeBzyJOgf1O80XQk37awS30nW8h6fHZeSRp4iZH1S9cDhR1wblySmCeVmnZUWlp0A 0B/g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id mj1si1034695ejb.54.2020.12.03.04.04.09; Thu, 03 Dec 2020 04:04:09 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388152AbgLCMDi (ORCPT + 6 others); Thu, 3 Dec 2020 07:03:38 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:9365 "EHLO szxga07-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726360AbgLCMDi (ORCPT ); Thu, 3 Dec 2020 07:03:38 -0500 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4CmvbR64ftz7861; Thu, 3 Dec 2020 20:02:27 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.9) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.487.0; Thu, 3 Dec 2020 20:02:44 +0800 From: Zhen Lei To: Philipp Zabel , Wei Xu , "Rob Herring" , linux-arm-kernel , devicetree , linux-kernel CC: Zhen Lei , Zhangfei Gao , Chen Feng , "Manivannan Sadhasivam" Subject: [PATCH 2/4] arm64: dts: correct vendor prefix hisi to hisilicon Date: Thu, 3 Dec 2020 20:02:10 +0800 Message-ID: <20201203120212.1105-3-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20201203120212.1105-1-thunder.leizhen@huawei.com> References: <20201203120212.1105-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.9] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The vendor prefix of "Hisilicon Limited" is "hisilicon", it is clearly stated in "vendor-prefixes.yaml". Fixes: 35ca8168133c ("arm64: dts: Add dts files for Hisilicon Hi3660 SoC") Fixes: dd8c7b78c11b ("arm64: dts: Add devicetree for Hisilicon Hi3670 SoC") Signed-off-by: Zhen Lei Cc: Chen Feng Cc: Manivannan Sadhasivam --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 4 ++-- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) -- 1.8.3 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 49c19c6879f95ce..bfb1375426d2b58 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -345,7 +345,7 @@ crg_rst: crg_rst_controller { compatible = "hisilicon,hi3660-reset"; #reset-cells = <2>; - hisi,rst-syscon = <&crg_ctrl>; + hisilicon,rst-syscon = <&crg_ctrl>; }; @@ -376,7 +376,7 @@ iomcu_rst: reset { compatible = "hisilicon,hi3660-reset"; - hisi,rst-syscon = <&iomcu>; + hisilicon,rst-syscon = <&iomcu>; #reset-cells = <2>; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 85b0dfb35d6d396..5c5a5dc964ea848 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -155,7 +155,7 @@ compatible = "hisilicon,hi3670-reset", "hisilicon,hi3660-reset"; #reset-cells = <2>; - hisi,rst-syscon = <&crg_ctrl>; + hisilicon,rst-syscon = <&crg_ctrl>; }; pctrl: pctrl@e8a09000 {