From patchwork Tue Dec 1 11:02:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 336208 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36B8DC64E7A for ; Tue, 1 Dec 2020 11:04:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C3FAF20809 for ; Tue, 1 Dec 2020 11:04:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="U27JUWr5" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730328AbgLALEd (ORCPT ); Tue, 1 Dec 2020 06:04:33 -0500 Received: from esa5.microchip.iphmx.com ([216.71.150.166]:63609 "EHLO esa5.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730317AbgLALEd (ORCPT ); Tue, 1 Dec 2020 06:04:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1606820673; x=1638356673; h=from:to:cc:subject:date:message-id:mime-version; bh=jauox//ePXwP8SQPPfgfnZWRrEQXHbn0G2vtEiP850Q=; b=U27JUWr5bEHRwxVzybzMckuZZ34eYSyVPCyEtH9IrUjPxKBFFtVqYD52 hAZw+qM48ZMDI0jRadWCuBWglxvozibDKnPaqaOMZmVUxyHwvrheMEMvX OuObXotZfTLLI/8iMnxphLVtMrRiL50OxQ3pEkYN39Dzi4QfQm22fYLeN yAjb3O+jQSYIN3CZLnCfFsqnMsYh3qzKU332ONaLYDJZo0lKBZU5tbJ9Y ImujKuOF6kbGeKkZKZ/C4/vzcH34GDa4k9XlMc6YzqHBUXe8T6xiwOe6H Vy6rpvcE2Cb/oKYkOveTS9g0xtFaBMToYmqGFvwlwdhIkqyqGenPy8EQp A==; IronPort-SDR: g7ol6B/HiOtIXty1iGzh01UtKvV2emKXDEs83RkaHo7bz43lfncXmP9GQlXcqriQuNgGrx+7cD EvvuJVWwr6QBw2Bi548AvMvl3erZgBvMcCdGMSDkxRpNUY57txYURhgG6hriS/3DBiLFhx7wUx b8+TvhT/SbnkGmczohjoRl9osVOckAEOP2ecCt5xz8XxvfBDr+oAtUmGGQoCe79/za/zNHmt6Y htnsLyCjcqp2VsNBiPKi1E18QxoHvQhEkrNoW9B8MLxoJq0PKZacUmN7BteaST2DPoN2O9sSUd J28= X-IronPort-AV: E=Sophos;i="5.78,384,1599548400"; d="scan'208";a="100384391" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Dec 2020 04:02:54 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Tue, 1 Dec 2020 04:02:53 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Tue, 1 Dec 2020 04:02:51 -0700 From: To: , , , , , , , CC: , , , , , , Conor Dooley Subject: [PATCH v2 2/5] dt-bindings: add bindings for polarfire soc mailbox Date: Tue, 1 Dec 2020 11:02:50 +0000 Message-ID: <20201201110250.28437-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Add device tree bindings for the MSS system controller mailbox on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley Reviewed-by: Rob Herring --- .../mailbox/microchip,mpfs-mailbox.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml diff --git a/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml new file mode 100644 index 000000000000..9c522a088d55 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/mailbox/microchip,mpfs-mailbox.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Microchip MPFS mss mailbox controller + +maintainers: + - Conor Dooley + +properties: + compatible: + const: microchip,polarfire-soc-mailbox + + reg: + items: + - description: mailbox data registers + - description: mailbox int registers + + interrupts: + maxItems: 1 + + "#mbox-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + mbox: mailbox@37020000 { + compatible = "microchip,polarfire-soc-mailbox"; + reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318c 0x0 0x40>; + interrupt-parent = <&L1>; + interrupts = <96>; + #mbox-cells = <1>; + }; + };