From patchwork Mon Nov 30 23:48:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 335295 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1D11C83011 for ; Mon, 30 Nov 2020 23:51:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6115520809 for ; Mon, 30 Nov 2020 23:51:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=permerror (0-bit key) header.d=wdc.com header.i=@wdc.com header.b="qtT08BmQ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388786AbgK3XvD (ORCPT ); Mon, 30 Nov 2020 18:51:03 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:7846 "EHLO esa2.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388821AbgK3XvD (ORCPT ); Mon, 30 Nov 2020 18:51:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1606780697; x=1638316697; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=S1YmWmqvdIYXxQKwYnEAtpW95Vpx9w6kjXteMcQR5RY=; b=qtT08BmQPG3Z+uHxOmDidjcOkqXETNKoivr5JYdvQ7DjeftIRoUkMsZn Ad6cdvLpd//FZ2lc7oGg89YE57plXRa4LMQbVO35AoUsOg/38/fczzwHO qcSZCAe7X+RGQZ7QtW1sTuhWU2d0sGPiF7tV6Ea/qei9PHUgH31tyFtEa ZcfasZpx5hxgdzSN5vAWJAmUEx7j/vtWZkAPHTCMVPxOwlAxN6sFlCJUS m2V0cVSaYMv6PMlhVfuqeGeCgB9VWAPLbwlXaqpmB9iSdCkkipDlQsMO0 EBaMKHvvGIfcvoObNjxzA/TOiNkLqrxnb+Fvv2AJMQZPr9i3x3SSrzQFA A==; IronPort-SDR: g7NnwGDmQ6D7jnnFZjcYDR8zjGwcX7DHaKnd4T05DqI37vb8/3xjRnb6TrfdnvuXYnZ8DWichz YP8cZUUwtjNdnt4805bhKwIXW/bHfdJ4BrQaAcuHu1X/9Yh5PhkK5OOMQ8EQT2IMjUj6cqMDA+ sdgLIk4uZtAQZCrlT1CKCpScx5t+48grM54p5ulmTpZDmBEZOS3vQPGPEhCG0hMMauqD4DpM+7 GW4ivorXgJFP3qE3Oura9+Ob11D405nHBdsjZMnoZ7hh5bMk3XniNI4eelHDvCj2uJRuS5OtuA Gs8= X-IronPort-AV: E=Sophos;i="5.78,382,1599494400"; d="scan'208";a="257538307" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 01 Dec 2020 07:54:57 +0800 IronPort-SDR: H/9/cC03Ld9Y+P8U0C7yWDkZ/mLQxus+Xvt7mdBT/17v/eh5Fcjh5njLb1gdPC5lxkooudBpbm C/Igi/V6QJvK+77LU0Nuo8L1bZuA9O+FE= Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Nov 2020 15:33:04 -0800 IronPort-SDR: mlgutMgSOQPWPDgpAFdgY+t/onvGnSCGs1F2SO/ILj6GB37Peu84VRFB1jHD3JcPqcJxCvAUwq 8/lCD4wkWJ9A== WDCIronportException: Internal Received: from phd004834.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.196]) by uls-op-cesaip01.wdc.com with ESMTP; 30 Nov 2020 15:48:49 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , devicetree@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH v3 08/21] dt-bindings: reset: Document canaan, k210-rst bindings Date: Tue, 1 Dec 2020 08:48:16 +0900 Message-Id: <20201130234829.118298-9-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201130234829.118298-1-damien.lemoal@wdc.com> References: <20201130234829.118298-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the device tree bindings for the Canaan Kendryte K210 SoC reset controller driver in Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml. The header file include/dt-bindings/reset/k210-rst.h is added to define all possible reset lines of the SoC. Signed-off-by: Damien Le Moal --- .../bindings/reset/canaan,k210-rst.yaml | 40 ++++++++++++++++++ include/dt-bindings/reset/k210-rst.h | 42 +++++++++++++++++++ 2 files changed, 82 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml create mode 100644 include/dt-bindings/reset/k210-rst.h diff --git a/Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml b/Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml new file mode 100644 index 000000000000..53e4ede9c0bd --- /dev/null +++ b/Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/canaan,k210-rst.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Canaan Kendryte K210 Reset Controller Device Tree Bindings + +maintainers: + - Damien Le Moal + +description: | + Canaan Kendryte K210 reset controller driver which supports the SoC + system controller supplied reset registers for the various peripherals + of the SoC. The K210 reset controller node must be defined as a child + node of the K210 system controller node. + + See also: + - dt-bindings/reset/k210-rst.h + +properties: + compatible: + const: canaan,k210-rst + + '#reset-cells': + const: 1 + +required: + - '#reset-cells' + - compatible + +additionalProperties: false + +examples: + - | + #include + sysrst: reset-controller { + compatible = "canaan,k210-rst"; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/reset/k210-rst.h b/include/dt-bindings/reset/k210-rst.h new file mode 100644 index 000000000000..883c1aed50e8 --- /dev/null +++ b/include/dt-bindings/reset/k210-rst.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Sean Anderson + * Copyright (c) 2020 Western Digital Corporation or its affiliates. + */ +#ifndef RESET_K210_SYSCTL_H +#define RESET_K210_SYSCTL_H + +/* + * Kendryte K210 SoC system controller K210_SYSCTL_SOFT_RESET register bits. + * Taken from Kendryte SDK (kendryte-standalone-sdk). + */ +#define K210_RST_ROM 0 +#define K210_RST_DMA 1 +#define K210_RST_AI 2 +#define K210_RST_DVP 3 +#define K210_RST_FFT 4 +#define K210_RST_GPIO 5 +#define K210_RST_SPI0 6 +#define K210_RST_SPI1 7 +#define K210_RST_SPI2 8 +#define K210_RST_SPI3 9 +#define K210_RST_I2S0 10 +#define K210_RST_I2S1 11 +#define K210_RST_I2S2 12 +#define K210_RST_I2C0 13 +#define K210_RST_I2C1 14 +#define K210_RST_I2C2 15 +#define K210_RST_UART1 16 +#define K210_RST_UART2 17 +#define K210_RST_UART3 18 +#define K210_RST_AES 19 +#define K210_RST_FPIOA 20 +#define K210_RST_TIMER0 21 +#define K210_RST_TIMER1 22 +#define K210_RST_TIMER2 23 +#define K210_RST_WDT0 24 +#define K210_RST_WDT1 25 +#define K210_RST_SHA 26 +#define K210_RST_RTC 29 + +#endif /* RESET_K210_SYSCTL_H */