From patchwork Mon Nov 30 23:48:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 334791 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85C0AC83017 for ; Mon, 30 Nov 2020 23:53:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 34781207BB for ; Mon, 30 Nov 2020 23:53:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=permerror (0-bit key) header.d=wdc.com header.i=@wdc.com header.b="pgAUuuFg" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389079AbgK3Xwy (ORCPT ); Mon, 30 Nov 2020 18:52:54 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:7901 "EHLO esa2.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389057AbgK3Xwx (ORCPT ); Mon, 30 Nov 2020 18:52:53 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1606780864; x=1638316864; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Rc2RSPnBRWY/myYpbOIzJhXLv/SU9F0BII0ZoItAbwA=; b=pgAUuuFgw5OIYyGqEuRU3QKh60VpzbZnro/2RAmyjN/nyXEM8UiIJ3la XmZb9drjPQEP4+y1WeGcYPq9S8+LqXwxJ9xwsvAvzIOoe9qeAWe1aQv2n xsS98h0WdNobJsO0dGQfZe4jdlAdbqa+QGcJS86CErFGoFGpGNdPt0yVT 3pCJ2atM2UzD2jjjo+hJVUAeBVvL5JdF3zx+MKIKlno7wvtkNp5KsgtWT bSDdXk+f5FQAdXlGaYvqVm2XXJy2OwF+M0oBAimK9bFF0Sj2aH46wP2TA xhNtDGWIDURHzKle+esUQZQljvBmAtTyGMuXrGNU/5+Mjvf5k45B5FaeA A==; IronPort-SDR: OC5jqLsYTmMBLwmBaplJJthnqAx2RUzYw0xzJDPKAClH1U0Vb/8K3LiRhfygNAdzo6Qmxt8h2f UkVa1QSFbagoGHNjsy2Cr+3kd/GI42IYnw5oReY7DH8wgugIYOoO0zODNwfrUCd2kPnMLWFlJN aycG/TIssCvsFAPIZlEcYXH2z5RnuSl0betL0/aSPkZhzEwRwhcFfeuae3V+2M51Q0DP4DOeDG GCDD3O7ZyUGOIuJQFb/jUs8w/c+9gJ5MiGfFjkUGeF1WfbKpar68UYQ1IyNIaljAToO/EA7biL A+s= X-IronPort-AV: E=Sophos;i="5.78,382,1599494400"; d="scan'208";a="257538347" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 01 Dec 2020 07:55:29 +0800 IronPort-SDR: 2D6t8Rct30ylfAwQQxUv7F4uGzbM4PyK+blPH885E8mt1fHtIS4ptOuSKwttw+apmDWdobt0W3 aeakKQFFQBDPI9Qk2G4hIiNkaLZiOxoHU= Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Nov 2020 15:33:24 -0800 IronPort-SDR: vMfGvY+/CPGMzjBUQmg7XxeUU1DJaHUIg3t+Nah7IsZ7sAkH1gntvBaCQT8HKDmgH88VC2QuI3 Lq0zx5KElbhQ== WDCIronportException: Internal Received: from phd004834.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.196]) by uls-op-cesaip01.wdc.com with ESMTP; 30 Nov 2020 15:49:09 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , devicetree@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH v3 18/21] riscv: Add SiPeed MAIXDUINO board device tree Date: Tue, 1 Dec 2020 08:48:26 +0900 Message-Id: <20201130234829.118298-19-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201130234829.118298-1-damien.lemoal@wdc.com> References: <20201130234829.118298-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a device tree for the SiPeed MAIXDUINO board. This device tree enables LEDs and spi/mmc SD card device. Additionally, gpios and i2c are also enabled and mapped to the board header pins as indicated on the board itself. Signed-off-by: Damien Le Moal --- arch/riscv/boot/dts/canaan/k210_maixduino.dts | 201 ++++++++++++++++++ 1 file changed, 201 insertions(+) create mode 100644 arch/riscv/boot/dts/canaan/k210_maixduino.dts diff --git a/arch/riscv/boot/dts/canaan/k210_maixduino.dts b/arch/riscv/boot/dts/canaan/k210_maixduino.dts new file mode 100644 index 000000000000..681f12b46894 --- /dev/null +++ b/arch/riscv/boot/dts/canaan/k210_maixduino.dts @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-20 Sean Anderson + * Copyright (C) 2020 Western Digital Corporation or its affiliates. + */ + +/dts-v1/; + +#include "k210.dtsi" + +#include +#include + +/ { + model = "SiPeed MAIXDUINO"; + compatible = "sipeed,maixduino", "canaan,kendryte-k210"; + + chosen { + bootargs = "earlycon console=ttySIF0"; + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + boot { + label = "BOOT"; + linux,code = ; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0 0>; + }; + + simple-audio-card,codec { + sound-dai = <&mic>; + }; + }; + + mic: mic { + #sound-dai-cells = <0>; + compatible = "memsensing,msm261s4030h0"; + status = "disabled"; + }; +}; + +&fpioa { + status = "okay"; + + uarths_pinctrl: uarths-pinmux { + pinmux = , /* Header "0" */ + ; /* Header "1" */ + }; + + gpio_pinctrl: gpio-pinmux { + pinmux = , + ; + }; + + gpiohs_pinctrl: gpiohs-pinmux { + pinmux = , /* BOOT */ + , /* Header "2" */ + , /* Header "3" */ + , /* Header "4" */ + , /* Header "5" */ + , /* Header "6" */ + , /* Header "7" */ + , /* Header "8" */ + , /* Header "9" */ + , /* Header "10" */ + , /* Header "11" */ + , /* Header "12" */ + ; /* Header "13" */ + }; + + i2s0_pinctrl: i2s0-pinmux { + pinmux = , + , + ; + }; + + spi1_pinctrl: spi1-pinmux { + pinmux = , + , + , + ; /* cs */ + }; + + i2c1_pinctrl: i2c1-pinmux { + pinmux = , /* Header "scl" */ + ; /* Header "sda" */ + }; + + i2s1_pinctrl: i2s1-pinmux { + pinmux = , + , + ; + }; + + spi0_pinctrl: spi0-pinmux { + pinmux = , /* cs */ + , /* rst */ + , /* dc */ + ; /* wr */ + }; + + dvp_pinctrl: dvp-pinmux { + pinmux = , + , + , + , + , + , + , + ; + }; +}; + +&uarths0 { + pinctrl-0 = <&uarths_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio0 { + pinctrl-0 = <&gpiohs_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio1 { + pinctrl-0 = <&gpio_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2s0 { + #sound-dai-cells = <1>; + pinctrl-0 = <&i2s0_pinctrl>; + pinctrl-names = "default"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pinctrl>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; + +&dvp0 { + pinctrl-0 = <&dvp_pinctrl>; + pinctrl-names = "default"; +}; + +&spi0 { + pinctrl-0 = <&spi0_pinctrl>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + + panel@0 { + compatible = "sitronix,st7789v"; + reg = <0>; + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio0 22 0>; + spi-max-frequency = <15000000>; + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_pinctrl>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio1_0 2 GPIO_ACTIVE_LOW>; + status = "okay"; + + slot@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + voltage-ranges = <3300 3300>; + spi-max-frequency = <25000000>; + broken-cd; + }; +}; + +&spi3 { + spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + broken-flash-reset; + }; +};