From patchwork Mon Nov 30 13:10:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 334826 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 291F2C83017 for ; Mon, 30 Nov 2020 13:12:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BF84520708 for ; Mon, 30 Nov 2020 13:12:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=0x0f.com header.i=@0x0f.com header.b="NOERfF7e" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726516AbgK3NM0 (ORCPT ); Mon, 30 Nov 2020 08:12:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35288 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726521AbgK3NMZ (ORCPT ); Mon, 30 Nov 2020 08:12:25 -0500 Received: from mail-pj1-x1043.google.com (mail-pj1-x1043.google.com [IPv6:2607:f8b0:4864:20::1043]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D486EC061A56 for ; Mon, 30 Nov 2020 05:11:20 -0800 (PST) Received: by mail-pj1-x1043.google.com with SMTP id b12so1339263pjl.0 for ; Mon, 30 Nov 2020 05:11:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=F4b6Mz+meeIOWiwdpvVizNGtENxtsbORSHHjjSCrlas=; b=NOERfF7egowMV6omqbGCYcnTmO++yhypJfIN0zzFCBLOwPjW5dSmvG0jSgPxeAESWL 9acj1SCmIXtpuCB2Z1uvcFa6v6k8VO8nec0r6OsyQX4L1rUrsewKlJ9uuqivdPfvvo5v MCSexCFH5DnPtbgd0TfpUvYMix7Q0BxgQoAjg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=F4b6Mz+meeIOWiwdpvVizNGtENxtsbORSHHjjSCrlas=; b=X7XdmPho2lmrvXowMhPwr8EurRyvarhoEOSwyq0sCM9lV5RVXdXQsRzTmepvg36afC LhvFiDm5cz0o6TyhIxSjSILo1JP6qATPgfzou8HDxUMYkRiSinpjHVkXKdWpBgOep+Ct /AB05/e9L+P3AOLgm5o+TyzbXm/sLoI+xTnEht4JvIHWyx+WpQym71ySP+5Q6CS0FEAy IK3mSxU3YgfzMOhuS8rAnBmUDOCtuKvkGQdVaNtWsh0wuh9IWSr4Km/qZ1ZBQuRxARKd Hf/G+/8K4bayvR0lClA+D1+O/N5NrqvKJkgfT8GQIBgjTcH3Pbfl0Y2vnht9ufUTgAOq 7kUQ== X-Gm-Message-State: AOAM533eO1DZpqH/2vivDXUdHsqHqAxUMqOkB8nPqx3d6u+WSVK1JkH+ xKtL78qgBZxSxzKIEwueD3I2P1fRYUHrMw== X-Google-Smtp-Source: ABdhPJytNtiSFjUBa/8hP6fMqYnvCTlKseq0Z9MVhm7I5h2NQTR5XgRtzFuTCSl6si+IwlkEQh6IOw== X-Received: by 2002:a17:90a:940c:: with SMTP id r12mr25793348pjo.201.1606741879985; Mon, 30 Nov 2020 05:11:19 -0800 (PST) Received: from shiro.work (p1268123-ipngn200803sizuokaden.shizuoka.ocn.ne.jp. [118.13.124.123]) by smtp.googlemail.com with ESMTPSA id a4sm41757578pjq.0.2020.11.30.05.11.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Nov 2020 05:11:19 -0800 (PST) From: Daniel Palmer To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, arnd@arndb.de, robh@kernel.org, w@1wt.eu, daniel@0x0f.com Subject: [PATCH 9/9] ARM: mstar: SMP support Date: Mon, 30 Nov 2020 22:10:47 +0900 Message-Id: <20201130131047.2648960-10-daniel@0x0f.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201130131047.2648960-1-daniel@0x0f.com> References: <20201130131047.2648960-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds SMP support for MStar/Sigmastar chips that have a second core like those in the infinity2m family. So far only single and dual core chips have been found so this does the bare minimum to boot the second core. From what I can tell not having the "holding pen" code to handle multiple cores is fine if there is only one core the will get booted. This might need to be reconsidered if chips with more cores turn up. Signed-off-by: Daniel Palmer --- arch/arm/mach-mstar/mstarv7.c | 50 +++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm/mach-mstar/mstarv7.c b/arch/arm/mach-mstar/mstarv7.c index 1aa748fa006e..23fe47a8f1a5 100644 --- a/arch/arm/mach-mstar/mstarv7.c +++ b/arch/arm/mach-mstar/mstarv7.c @@ -31,6 +31,13 @@ #define MSTARV7_L3BRIDGE_FLUSH_TRIGGER BIT(0) #define MSTARV7_L3BRIDGE_STATUS_DONE BIT(12) +#ifdef CONFIG_SMP +#define MSTARV7_CPU1_BOOT_ADDR_HIGH 0x4c +#define MSTARV7_CPU1_BOOT_ADDR_LOW 0x50 +#define MSTARV7_CPU1_UNLOCK 0x58 +#define MSTARV7_CPU1_UNLOCK_MAGIC 0xbabe +#endif + static void __iomem *l3bridge; static const char * const mstarv7_board_dt_compat[] __initconst = { @@ -63,6 +70,46 @@ static void mstarv7_mb(void) } } +#ifdef CONFIG_SMP +static int mstarv7_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + struct device_node *np; + u32 bootaddr = (u32) __pa_symbol(secondary_startup_arm); + void __iomem *smpctrl = 0; + + /* + * right now we don't know how to boot anything except + * cpu 1. + */ + if (cpu != 1) + return -EINVAL; + + np = of_find_compatible_node(NULL, NULL, "mstar,smpctrl"); + smpctrl = of_iomap(np, 0); + + if (!smpctrl) + return -ENODEV; + + /* set the boot address for the second cpu */ + writew(bootaddr & 0xffff, smpctrl + MSTARV7_CPU1_BOOT_ADDR_LOW); + writew((bootaddr >> 16) & 0xffff, smpctrl + MSTARV7_CPU1_BOOT_ADDR_HIGH); + + /* unlock the second cpu */ + writew(MSTARV7_CPU1_UNLOCK_MAGIC, smpctrl + MSTARV7_CPU1_UNLOCK); + + /* and away we go...*/ + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); + + iounmap(smpctrl); + + return 0; +} + +struct smp_operations __initdata mstarv7_smp_ops = { + .smp_boot_secondary = mstarv7_boot_secondary, +}; +#endif + static void __init mstarv7_init(void) { struct device_node *np; @@ -78,4 +125,7 @@ static void __init mstarv7_init(void) DT_MACHINE_START(MSTARV7_DT, "MStar/Sigmastar Armv7 (Device Tree)") .dt_compat = mstarv7_board_dt_compat, .init_machine = mstarv7_init, +#ifdef CONFIG_SMP + .smp = smp_ops(mstarv7_smp_ops), +#endif MACHINE_END