From patchwork Thu Nov 26 07:21:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 332922 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp1091508ilb; Wed, 25 Nov 2020 23:24:43 -0800 (PST) X-Google-Smtp-Source: ABdhPJzGS7APkTMebGA7Qcpvh5i9xqAoHm0ySleUr0ck9PAdHPKUnLpyyVVbIhmayjAd4E/t4KM1 X-Received: by 2002:a17:906:37cb:: with SMTP id o11mr1517789ejc.10.1606375482925; Wed, 25 Nov 2020 23:24:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606375482; cv=none; d=google.com; s=arc-20160816; b=oQBDjsM/kdF/sBVCw+/ekoLp/sBEBZPBvsQDMt4N12o6m7WeeVUPzz7OavK2Dx73qa s9hPVJCF+dAki5rjWW1CJ0ixheyQz8VBXDIY9W/v12Cbhai8lFlBnrzKQ6gNRaDI0974 k/fP4DU1aWnM/XAL8r0bTlpJIcFSYGFWyaRaqhofxiOsAV5nzxXjdsX2zN4jOJQr0ouB m1qqd/olWRi1hXhObjDkriFEawSj8y/mk3w762HsaGng+nbLQ/FRWBn8IX4nW/pSCRS0 sbF/YcCBSEzJBohPJk6RLqlfRchR7GMVYkCqbKJ+Ti+cxaH1YM969R5TNVNAUsx8a6tp 4s1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=DrIF8npwlrqxLr6Igah5Ek/omJmCk/eZLSe1ULAbqaY=; b=NB0a15wFgn8rLIR0DRvywrOke9kHtJiIFY7RHsP21KvjGW3+Vuk9G0NsBEx8N+N1Mq F5noUpvMTengRLjWxtl+Bocv8fOKuqJIRaFjJh6MugMxbHV8W8dfn6TlY8gV1adxTGvd wYKicxU+CaM6PeAmA3gdyBqVJscxU8ShSTcUV2jvH10yWHzoMrVFlsZZwC7gxk8mXWkK 5eEQY8acIaHJ/4ectlmxOIiOou9/AbOtuWoNW6Evx+04bk7RsXnFraKGMvTTF2xCfVa0 yEYTZaBa+7na7wkPHiLciyxsxW95bPIx8EFifr+yVJlwMnAsIG8ekWGLhgxCJ0UbGhNn GWFg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id y11si2875812edp.494.2020.11.25.23.24.42; Wed, 25 Nov 2020 23:24:42 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388495AbgKZHYQ (ORCPT + 6 others); Thu, 26 Nov 2020 02:24:16 -0500 Received: from mail.kernel.org ([198.145.29.99]:41954 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388477AbgKZHYQ (ORCPT ); Thu, 26 Nov 2020 02:24:16 -0500 Received: from localhost.localdomain (unknown [157.49.218.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 4F48B2068D; Thu, 26 Nov 2020 07:23:56 +0000 (UTC) From: Manivannan Sadhasivam To: sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org Cc: bjorn.andersson@linaro.org, vkoul@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v4 5/6] dt-bindings: clock: Add GDSC in SDX55 GCC Date: Thu, 26 Nov 2020 12:51:45 +0530 Message-Id: <20201126072146.34842-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201126072146.34842-1-manivannan.sadhasivam@linaro.org> References: <20201126072146.34842-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add GDSC instances in SDX55 GCC block. Signed-off-by: Manivannan Sadhasivam --- include/dt-bindings/clock/qcom,gcc-sdx55.h | 5 +++++ 1 file changed, 5 insertions(+) -- 2.25.1 diff --git a/include/dt-bindings/clock/qcom,gcc-sdx55.h b/include/dt-bindings/clock/qcom,gcc-sdx55.h index c372451b3461..fb9a5942f793 100644 --- a/include/dt-bindings/clock/qcom,gcc-sdx55.h +++ b/include/dt-bindings/clock/qcom,gcc-sdx55.h @@ -109,4 +109,9 @@ #define GCC_USB3PHY_PHY_BCR 13 #define GCC_USB_PHY_CFG_AHB2PHY_BCR 14 +/* GCC power domains */ +#define USB30_GDSC 0 +#define PCIE_GDSC 1 +#define EMAC_GDSC 2 + #endif