From patchwork Mon Nov 9 06:26:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 320900 Delivered-To: patch@linaro.org Received: by 2002:a92:7b12:0:0:0:0:0 with SMTP id w18csp1497915ilc; Sun, 8 Nov 2020 22:26:37 -0800 (PST) X-Google-Smtp-Source: ABdhPJwkzqwN1LXZnKUOfva6VSHZJ43ZLlX6q2PQ6L7xX4koz+uX47LEez3gx6MPmnMua+YOyMY7 X-Received: by 2002:a05:6402:129a:: with SMTP id w26mr14143754edv.192.1604903197041; Sun, 08 Nov 2020 22:26:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1604903197; cv=none; d=google.com; s=arc-20160816; b=XEdFES9kRwrq/f//X88+CXOsjoJdVyuszgPA8liBuFV3555wbCQO7LgWpDT3yGjoPi 9IuCxq23l14579kH7GZFvYYqo4h4N4UduxKB0qgwRAEr57NsQgsk3QHk7wG/y7HsY275 3+UTib644oSPD2wMvUrsPuZWhpyOz80oO3S7do8WKqMc6mOdntIUGd79p3B1THvOqgea fsUKMf8AqA5RtOR4OMYVds3nAAfVS2ZWTS6rl1qgV6LG8uWoBqBIGuO71iIK7oQCFLBu COtEv/kQ8TIvHkETBz3CspoExt5ufOp/kNNgXEbVzui8/gtSmmZ5RO+htP/e1JI8MwLr vF0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=hBOdTaF/EbZmoNye9ooMyf8WFkagkD3juUyWLfdCa04=; b=G5sIubWgm0zOgQDeEfI5x+VbDLpur2BO7cXopuppz3SZsmvHK+/kBLlV5BvM6XDtbS CYliACdTzDeOIG1w6juSOYP7FC60La72DAhBf6K6QRc9lNPdwR893C7fIYrsEjsNcX57 YFdIVYX+SrWU5tC57wX+Qs5Da+bVOXnDTUTajr9RQqZoe8nRW4g1MqDic/UfC7ruEb3A 83zFATAn6fUeBv1i2xOE0jCsZ4wz0tUg82q3Gpo5htKPY59AjSCyNCZhmi9+T7Fit7Bf ncbkf8Vrls7ZV+M8K34H0FDrjX+gnPFQMEjNRSM/9p8A3sHql0bLvaHPzREciXRFQmN/ LvhA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=RNOmKnvG; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id r16si6512157edq.149.2020.11.08.22.26.36; Sun, 08 Nov 2020 22:26:37 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=RNOmKnvG; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729571AbgKIG0g (ORCPT + 6 others); Mon, 9 Nov 2020 01:26:36 -0500 Received: from mail.kernel.org ([198.145.29.99]:33364 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729561AbgKIG0g (ORCPT ); Mon, 9 Nov 2020 01:26:36 -0500 Received: from localhost.localdomain (unknown [122.171.147.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 42343206E5; Mon, 9 Nov 2020 06:26:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1604903194; bh=Dazq1m38JSr4fzbVjXrSuwf6X2T/qSo+SXyemXJichw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RNOmKnvGbNkBBjx2WtYrngpfYUhxVilg/TZHRKcSjLFqfkzg5X2sVkCVAfO5yEYA6 Oo/tTMnB1HvXBmCyblQe7fmhnLuRY33CaslJ6rmkPjLAn9hGrtHK7LzQ5RRcmRuKxd M5NbFvmpaYRUbOoEyuGSmS4srR/Rl2CuSrNpE0g4= From: Vinod Koul To: Linus Walleij Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , Andy Gross , Rob Herring , Manivannan Sadhasivam , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/2] dt-bindings: pinctrl: qcom: Add SDX55 pinctrl bindings Date: Mon, 9 Nov 2020 11:56:19 +0530 Message-Id: <20201109062620.14566-2-vkoul@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201109062620.14566-1-vkoul@kernel.org> References: <20201109062620.14566-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device tree binding Documentation details for Qualcomm SDX55 pinctrl driver. Reviewed-by: Bjorn Andersson Signed-off-by: Vinod Koul --- .../bindings/pinctrl/qcom,sdx55-pinctrl.yaml | 154 ++++++++++++++++++ 1 file changed, 154 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml -- 2.26.2 diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml new file mode 100644 index 000000000000..112dd59ce7ed --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml @@ -0,0 +1,154 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sdx55-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SDX55 TLMM block + +maintainers: + - Vinod Koul + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + SDX55 platform. + +properties: + compatible: + const: qcom,sdx55-pinctrl + + reg: + description: Specifies the base address and size of the TLMM register space + maxItems: 1 + + interrupts: + description: Specifies the TLMM summary IRQ + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + description: Specifies the PIN numbers and Flags, as defined in + include/dt-bindings/interrupt-controller/irq.h + const: 2 + + gpio-controller: true + + '#gpio-cells': + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-reserved-ranges: + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: "/schemas/pinctrl/pincfg-node.yaml" + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-6])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. Functions are only valid for gpio pins. + enum: [ adsp_ext, atest, audio_ref, bimc_dte0, bimc_dte1, blsp_i2c1, + blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_spi1, blsp_spi2, + blsp_spi3, blsp_spi4, blsp_uart1, blsp_uart2, blsp_uart3, + blsp_uart4, char_exec, coex_uart, coex_uart2, cri_trng, + cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, + ebi0_wrcdc, ebi2_a, ebi2_lcd, emac_gcc0, emac_gcc1, + emac_pps0, emac_pps1, ext_dbg, gcc_gp1, gcc_gp2, gcc_gp3, + gcc_plltest, gpio, i2s_mclk, jitter_bist, ldo_en, ldo_update, + mgpi_clk, m_voc, native_char, native_char0, native_char1, + native_char2, native_char3, native_tsens, native_tsense, + nav_gpio, pa_indicator, pcie_clkreq, pci_e, pll_bist, pll_ref, + pll_test, pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, + qdss_gpio0, qdss_gpio1, qdss_gpio2, qdss_gpio3, qdss_gpio4, + qdss_gpio5, qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9, + qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, + qdss_gpio14, qdss_gpio15, qdss_stm0, qdss_stm1, qdss_stm2, + qdss_stm3, qdss_stm4, qdss_stm5, qdss_stm6, qdss_stm7, + qdss_stm8, qdss_stm9, qdss_stm10, qdss_stm11, qdss_stm12, + qdss_stm13, qdss_stm14, qdss_stm15, qdss_stm16, qdss_stm17, + qdss_stm18, qdss_stm19, qdss_stm20, qdss_stm21, qdss_stm22, + qdss_stm23, qdss_stm24, qdss_stm25, qdss_stm26, qdss_stm27, + qdss_stm28, qdss_stm29, qdss_stm30, qdss_stm31, qlink0_en, + qlink0_req, qlink0_wmss, qlink1_en, qlink1_req, qlink1_wmss, + spmi_coex, sec_mi2s, spmi_vgi, tgu_ch0, uim1_clk, uim1_data, + uim1_present, uim1_reset, uim2_clk, uim2_data, uim2_present, + uim2_reset, usb2phy_ac, vsense_trigger ] + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + required: + - pins + - function + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + tlmm: pinctrl@1f00000 { + compatible = "qcom,sdx55-pinctrl"; + reg = <0x0f100000 0x300000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 108>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + + serial-pins { + pins = "gpio8", "gpio9"; + function = "blsp_uart3"; + drive-strength = <8>; + bias-disable; + }; + }; + +...