From patchwork Wed Nov 4 13:29:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 320529 Delivered-To: patch@linaro.org Received: by 2002:a92:7b12:0:0:0:0:0 with SMTP id w18csp5438749ilc; Wed, 4 Nov 2020 05:29:24 -0800 (PST) X-Google-Smtp-Source: ABdhPJxVQ3qoJV4lQ22oPGGg/9Ob/4Ai0FGnMxdbu8IaGHckt3IjtjZ4yG6rhpmh5oUx5ssHjySQ X-Received: by 2002:a17:906:cd0f:: with SMTP id oz15mr25148719ejb.200.1604496564078; Wed, 04 Nov 2020 05:29:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1604496564; cv=none; d=google.com; s=arc-20160816; b=Oc/1JddAcINQGG+llj+tq6xLbHnuSl+E3JbzdQ+sgTeCbSAkA0HT5d8mkeGxfwORem 7xaDG0fMkIJYWpOnKq/rLM87VkCdgG2/r3WduytRkkO7QjCAXv4uzmtqfbuxotyhck38 4/WxeAIkIucMhGjUkg9hWlW3mTcxT+/9+lNGJH9IdUOADk5NfR0lSaKZC7rZRLitKmmy +Gkie8kl/A+znQBgkPMr+eCixerZyoQ/Sp+nhQ2eLnopoNZQgZEIHdfFx9nNXkkPk6K3 xg2VQDBce8LmBzMbbO1TrH09biwgXnQ2/OCCc5BFJctHL/xzLZtn5Cbw38I0BXMymEua FLbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=PtHXF2cHPApTNeqeYgINKJbCjjOgLe/T5YN49wwC7u4=; b=qHUef6Zo9YWa++qFPj0PGaQe8z36fxvS9HgtNCuueAKqXQowqyuy11JyNRqzMLOO/4 32uMs579eYF6krfj+eY/sVySfbFXzRd/aT6TZqyHAHyEYqwQjnyl39qw0uJB9hBbiRso RXP1TRF3P6EJ9OjPdFqj/ci8eCRLKQAm1ZhCHqzN5HPn0wVoX/ekFQauEBNPsX621yAA PvixSplrgIFKr+FqJVfd6VlaKNN7+Gn46OS0mRqcXFGPNy8Ag42PG1zMPBEC384nJ+gV 1ypFY5Mjtxz8xqTKTSdG/DLHrtX8hF/awRRbDZr6zZTUtsSaKbvEjAEGSw99KsYZ/q5z TCCw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="MNN/X2Zp"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id ml22si1352158ejb.172.2020.11.04.05.29.23; Wed, 04 Nov 2020 05:29:24 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="MNN/X2Zp"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730064AbgKDN3T (ORCPT + 6 others); Wed, 4 Nov 2020 08:29:19 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:52506 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729794AbgKDN3S (ORCPT ); Wed, 4 Nov 2020 08:29:18 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0A4DTDPr012554; Wed, 4 Nov 2020 07:29:13 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1604496553; bh=PtHXF2cHPApTNeqeYgINKJbCjjOgLe/T5YN49wwC7u4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=MNN/X2ZpOaRXCflScA6XPjGvI80o4qRIyADwyd6u6QTOZPWmqFPWNHnWqSLscXbGY dcaj4wsjvdZ5sbj6HHLnz49tzdkoD9xQUt71iz06BHxlHaVL3VMoepP14YN1kwqdjp HHs5pkqjEn/rqZk3CuSNiisu9CDwFuEGg/0rMhuc= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0A4DTDUg110417 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 4 Nov 2020 07:29:13 -0600 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 4 Nov 2020 07:29:13 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 4 Nov 2020 07:29:13 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0A4DT3nG024388; Wed, 4 Nov 2020 07:29:10 -0600 From: Kishon Vijay Abraham I To: Tero Kristo , Nishanth Menon , Rob Herring , Roger Quadros CC: Kishon Vijay Abraham I , , , Subject: [PATCH 2/2] arm64: dts: ti: k3-j721e-common-proc-board: Re-name "link" name as "phy" Date: Wed, 4 Nov 2020 18:59:02 +0530 Message-ID: <20201104132902.20377-3-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201104132902.20377-1-kishon@ti.com> References: <20201104132902.20377-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Commit 66db854b1f62d ("arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances") and commit 02c35dca2b488 ("arm64: dts: ti: k3-j721e: Enable Super-Speed support for USB0") added PHY DT nodes with node name as "link" However nodes with #phy-cells should be named 'phy'. Re-name subnodes of serdes in J721E to 'phy'. Link: http://lore.kernel.org/r/20200909203631.GA3026331@bogus Link: http://lore.kernel.org/r/1603898561-5142-1-git-send-email-sjakhade@cadence.com Fixes: 66db854b1f62d ("arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances") Fixes: 02c35dca2b488 ("arm64: dts: ti: k3-j721e: Enable Super-Speed support for USB0") Signed-off-by: Kishon Vijay Abraham I --- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 52e121155563..e837614d8d88 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -325,7 +325,7 @@ }; &serdes3 { - serdes3_usb_link: link@0 { + serdes3_usb_link: phy@0 { reg = <0>; cdns,num-lanes = <2>; #phy-cells = <0>; @@ -561,7 +561,7 @@ }; &serdes0 { - serdes0_pcie_link: link@0 { + serdes0_pcie_link: phy@0 { reg = <0>; cdns,num-lanes = <1>; #phy-cells = <0>; @@ -571,7 +571,7 @@ }; &serdes1 { - serdes1_pcie_link: link@0 { + serdes1_pcie_link: phy@0 { reg = <0>; cdns,num-lanes = <2>; #phy-cells = <0>; @@ -581,7 +581,7 @@ }; &serdes2 { - serdes2_pcie_link: link@0 { + serdes2_pcie_link: phy@0 { reg = <0>; cdns,num-lanes = <2>; #phy-cells = <0>;