From patchwork Tue Oct 27 17:00:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 319193 Delivered-To: patch@linaro.org Received: by 2002:a92:7b12:0:0:0:0:0 with SMTP id w18csp1746500ilc; Tue, 27 Oct 2020 10:01:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxfU+FjE9tdaleyjDscqGExYQBAagynfkvBOV3D3dqdjW+pdDuSVgkQplojrNwfj1aiYSy7 X-Received: by 2002:aa7:dc42:: with SMTP id g2mr3256145edu.11.1603818070386; Tue, 27 Oct 2020 10:01:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1603818070; cv=none; d=google.com; s=arc-20160816; b=TgFtaQ8pa6Qz36ZdFihWgVMwAYIDjlVnmBlNBgIs5+39Lf4sZU8ubExah02L5B81Y1 f8o9WimlI+J7XEkhpmLpZWfkiyvs58I9nGbj+oOsyKm+OPi8RSBC3pFpjpH4Bl3CW7vx B6cWzL4OM8pEQ3Epz3+FlP/DP/ogDC3qdhkG/w7ZkXcBbtwj39Bx9YPkPeH4PUq/Klm6 gMh8Q5ifw8c3De+DHh3VreAlkHHrfV8GfHJf1BSZNjYlxefWvc/EEV1ejCBAREqH3gO7 L9lrYsJ2RPFTaM78AHnTJYeCntQpyQfjqHQYuRMfuezCOkvguToFg8hE8AS/N3d9GstF aJdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=TNXeOK9vUsEFI4JUtV4egM0DUSZSe3itu2u2LWkjX5w=; b=QWckVxWlemGYwdObHIx8rhhXOES4tvCON31nTvxPjhpmz9yfsuPpWkKow0pSKVI6Ko XACqVIMUNzfzpVDN9k4gZdrpYppJbaKGzqh8NMSrhgoOaLRUzz619vXuy6L0vZog9C0p +jxyXfcCLdVoMBAzeUi0ynKISVZHiNqjtBVkR6GMafMd4qwCxkUSoZTuwfLbtUYfni2o rZAEHUKTbTlBLKadAchlaT3zQj19Ow4ecuDmskUxoRMLNKx+jLM8ltnPTH2ZBLi6Vis3 kpcBO/Jgskwxfjehnz83Q5DKjm8gy8wDra7jKg4ugE0BZou0VugcQf5bpdzhU3Nw0owo 6BWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aEMqKfkT; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id dp16si1571288ejc.178.2020.10.27.10.01.10; Tue, 27 Oct 2020 10:01:10 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aEMqKfkT; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1814978AbgJ0RBF (ORCPT + 6 others); Tue, 27 Oct 2020 13:01:05 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:42356 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1814989AbgJ0RBF (ORCPT ); Tue, 27 Oct 2020 13:01:05 -0400 Received: by mail-pl1-f195.google.com with SMTP id t22so1075643plr.9 for ; Tue, 27 Oct 2020 10:01:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TNXeOK9vUsEFI4JUtV4egM0DUSZSe3itu2u2LWkjX5w=; b=aEMqKfkT0Tl54TdvizwSl1oWEYp2e7iPH1MXyWg+e/USxQFZWVKLmrwvY8KHxKebWp 2vB7F3XhieXq1nuljcqigZMG6Prc407PDbqs22U/jSHiU+XjxzBUYIOk7qJbPbQZHDXT lXdBwjmj0bylYMp9Kst2VJWpbmCa2XfyOWeOHucC6EpGsrLn1TWHPf2gdFZXfu4B+NDf L7SiUtqYY6IgS8+9OH8uGxdazQhJfcC0KHN/JBULOqLHzgO0JpRe5PAHdU1HwXsSKeaW c2zN2SXO0m4or2QyiYPqnXMZlsTaQBsMB5AJ+3i8IwkWPde/8moIlQ4Jinqfc68Aer/Z B07g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TNXeOK9vUsEFI4JUtV4egM0DUSZSe3itu2u2LWkjX5w=; b=OhX9oj0oUt8sxmh2KjLBZr6I6sTDN7Ktj/CapSG9kitJT7vOquGfZBJ5JRpjisP2/3 ligi6Eq5bfU4bdxvCawIFJ6oz3bK/QJqDGYSOeFo2UQ1EsO9RPbkmAm0rcVAGw9PZGU1 2uA8xuACGJ6Gc7BHelEjGEeV/rf3X2cDVj+THo9Gx7avFN3fSrFOVStikGXDtO2IqlCR iXNAN1TiXpqIgJYGHUyetfqS5h3cyXEZ8pAFWJ5HOAkPhOluMzuXUMu2EVRsAMxN0YOY rkl8pG1gk4j/TLmwK6XdTURLeEA35HDNGfD1S8EU9xadFWYhy9KYWtdsci1DsSSdEsvP FC/g== X-Gm-Message-State: AOAM5328ZBZ91RvxoborNjlLjdg3I+Mk0t3LStUcHlIQbdH8CjtlymVt o6la3W0rKHIhwxX3FCdYW8WRDDgKwj/7dgU= X-Received: by 2002:a17:90a:3fcd:: with SMTP id u13mr2893644pjm.85.1603818064234; Tue, 27 Oct 2020 10:01:04 -0700 (PDT) Received: from localhost.localdomain ([103.59.133.81]) by smtp.googlemail.com with ESMTPSA id x26sm2845206pfn.178.2020.10.27.10.01.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Oct 2020 10:01:03 -0700 (PDT) From: Manivannan Sadhasivam To: agross@kernel.org, bjorn.andersson@linaro.org, kishon@ti.com, vkoul@kernel.org, robh@kernel.org Cc: svarbanov@mm-sol.com, bhelgaas@google.com, lorenzo.pieralisi@arm.com, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, mgautam@codeaurora.org, devicetree@vger.kernel.org, truong@codeaurora.org, Manivannan Sadhasivam Subject: [PATCH v5 4/5] PCI: qcom: Add SM8250 SoC support Date: Tue, 27 Oct 2020 22:30:32 +0530 Message-Id: <20201027170033.8475-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201027170033.8475-1-manivannan.sadhasivam@linaro.org> References: <20201027170033.8475-1-manivannan.sadhasivam@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The PCIe IP (rev 1.9.0) on SM8250 SoC is similar to the one used on SDM845. Hence the support is added reusing the members of ops_2_7_0. The key difference between ops_2_7_0 and ops_1_9_0 is the config_sid callback, which will be added in successive commit. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring --- drivers/pci/controller/dwc/pcie-qcom.c | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.17.1 Reviewed-by: Bjorn Andersson diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index b4761640ffd9..0b180a19b0ea 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1361,6 +1361,16 @@ static const struct qcom_pcie_ops ops_2_7_0 = { .post_deinit = qcom_pcie_post_deinit_2_7_0, }; +/* Qcom IP rev.: 1.9.0 */ +static const struct qcom_pcie_ops ops_1_9_0 = { + .get_resources = qcom_pcie_get_resources_2_7_0, + .init = qcom_pcie_init_2_7_0, + .deinit = qcom_pcie_deinit_2_7_0, + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, + .post_init = qcom_pcie_post_init_2_7_0, + .post_deinit = qcom_pcie_post_deinit_2_7_0, +}; + static const struct dw_pcie_ops dw_pcie_ops = { .link_up = qcom_pcie_link_up, }; @@ -1474,6 +1484,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 }, { .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 }, { .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 }, + { .compatible = "qcom,pcie-sm8250", .data = &ops_1_9_0 }, { } };