From patchwork Mon Oct 12 13:17:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 317636 Delivered-To: patch@linaro.org Received: by 2002:a92:d603:0:0:0:0:0 with SMTP id w3csp4616940ilm; Mon, 12 Oct 2020 06:20:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyV+bXC7xF1TqVlus3HC4YJpiLx/EOhX8/BLRgh7IA3fd2Mc51KKtQ5SLtsTtBr9guO3aun X-Received: by 2002:a17:906:d964:: with SMTP id rp4mr802689ejb.110.1602508812315; Mon, 12 Oct 2020 06:20:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1602508812; cv=none; d=google.com; s=arc-20160816; b=SdviD8USo0ds7sXjp+wdHrMfjTZIM2Or9l71wCcOCng5lSZEf40yWoldSbJTllIXgj UZeQGvcTlsPOCpOmDvJy39rQFO+mXWzvsISLZYLMdnZmGx22ts0KIqw2oDQq4ydkFtmN LsPbWrRSRV6/rgEgwkGMkN2OTMoXtOC+GGmZDTEJybLml2iA0EerLvxbNrtisA3GkzkO XwRCFvcx+RlNVe5a1IC/2TVKxfASPjRlZozWgUeBXvD7xXMT8O47w1qSehKFo/pZgZPX g8/xTu3q9jLz1DOYLlDwHWFNiUx5OdlL5ALCsldQpqJ4mGJh7wQdVO3SyFF3tlVmauhB z/5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=9zop6Rw5JSGx3E+ApZcWr60zeHb+sDC9FfK4QtKUlhg=; b=Zec2YyWKCqRUjPMW7GkFIwCR3RBX4LbDQCZiIkdlFFQLmZtTYD39eszf8DHYOaMYb7 A1itw5WRvKb3jVEQOUa3zangLyTCd2orNFaMAbhHA1SS9k0n4nr6uZbwUgBlCRYGKKOq 6NGjsDxbgtu8WXmeGAqoC52J0W7Hn737Q8R2TNy6xX3q8vo8bG6rdG0e6YePS17mQf4F eBu/p0XqGxmnPTVxL5ZVL3Vdcb837O4gU02QNrMYMNOBh7TSoIf5+Cw769XwAlGHb8Q1 Mj9lnUh+aiwJS/RjSND84n4294FvCqwoWAwiNR1r19b0uJuh7Owo1Og9FkYutMGOrSz6 yBeQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id dp1si12424524ejc.606.2020.10.12.06.20.12; Mon, 12 Oct 2020 06:20:12 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388976AbgJLNUB (ORCPT + 6 others); Mon, 12 Oct 2020 09:20:01 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:15278 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2388891AbgJLNTh (ORCPT ); Mon, 12 Oct 2020 09:19:37 -0400 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id C55411CB2D0619CA4B7E; Mon, 12 Oct 2020 21:19:35 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.134) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.487.0; Mon, 12 Oct 2020 21:19:28 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei Subject: [PATCH 10/11] arm64: dts: hisilicon: list all clocks required by pl011.yaml Date: Mon, 12 Oct 2020 21:17:38 +0800 Message-ID: <20201012131739.1655-11-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20201012131739.1655-1-thunder.leizhen@huawei.com> References: <20201012131739.1655-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.134] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The arm,pl011 binding need to specify two clocks: "uartclk", "apb_pclk". But only "apb_pclk" is specified now. Because the driver preferentially matches the first clock. Otherwise, it matches the second clock instead of both clocks. So both of them use the same clock don't change the function. Signed-off-by: Zhen Lei --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 1.8.3 diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index 1c7dda972c92856..81d09434c5c610d 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -216,8 +216,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x8b00000 0x1000>; interrupts = ; - clocks = <&sysctrl HISTB_UART0_CLK>; - clock-names = "apb_pclk"; + clocks = <&sysctrl HISTB_UART0_CLK>, <&sysctrl HISTB_UART0_CLK>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; @@ -225,8 +225,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x8b02000 0x1000>; interrupts = ; - clocks = <&crg HISTB_UART2_CLK>; - clock-names = "apb_pclk"; + clocks = <&crg HISTB_UART2_CLK>, <&crg HISTB_UART2_CLK>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; };