From patchwork Mon Oct 12 06:12:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 317623 Delivered-To: patch@linaro.org Received: by 2002:a92:d603:0:0:0:0:0 with SMTP id w3csp4332698ilm; Sun, 11 Oct 2020 23:13:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzeZe3S6wg+eZT8mDzRACyUkvhfHqhrOlX7L6ggdtoLp/CXF29+wCHNSHmHPLgehvYiXbf0 X-Received: by 2002:a50:d84f:: with SMTP id v15mr12058834edj.61.1602483204883; Sun, 11 Oct 2020 23:13:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1602483204; cv=none; d=google.com; s=arc-20160816; b=yNS6CnIivQSn0O2wzWwvrpGqan6kB8THtesVcvzbFJU0BCbzpHX6EU8ztiOnZuzf/U KKxizKKzz7gyZNoKi1j/U3OpH9swHJBu7B78KfFSjpmUDbL7vXsSyLikxVvMYyXcwRY5 4LYHFvLE92wk/c5yQRpwMVWFVV0+dStKkg8iw9JCneV9Swc1o5qBfvejqjtqXbMGiEv2 nmFDqkWHut9VP8EFWooNtHdddEMIG3YCWWz0js9jHbd8dEGBWc5nwHEEL8+oxn6Cris5 9Qk3tOKJ1WpOj89vm6rRciYlYB/EADiVVDz/Szk2++padT5GWgi4bzWQ9HdFKl+XDdte ghQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=kL4onZ79jRTGY1zSp3AoIXTyK/wHoyJXcM88vYmzjTA=; b=Te8AcExFKHROaB+vBKarCuv0gTUNwcaaSpAnhFwmgYjoluIeKPNycgRl6gkjfhtg9P 5xxIjDDiBSE4wmgBdPYoys8pQ8/BP5Orvyz/cHgyHaoc4TfaIqg1d/HTJ4uaqbBUCSPi +CMyY2p/6vAZse6GpYXONbe2xZi8zjHyG9tgY3DA/UaxY8YRwu/xfAFTmlPjY1ViUD95 B5Tfqw6JxgSc6mugnmS2yQRR+tvxZTGLFxQYzGEuVq9ZYOcsFHWA8qS1GbP//LTiMXTg OCfDSRMtkhCcnrfVgoAiTACV4uZkEW9zbN9cP38FCzkBobZ32E1XwfDClTXrc1711ZOA KxQw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id pg3si13843761ejb.685.2020.10.11.23.13.24; Sun, 11 Oct 2020 23:13:24 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727386AbgJLGNE (ORCPT + 6 others); Mon, 12 Oct 2020 02:13:04 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:45554 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727337AbgJLGM5 (ORCPT ); Mon, 12 Oct 2020 02:12:57 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id C3802C80DC9FBB15F377; Mon, 12 Oct 2020 14:12:50 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.134) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Mon, 12 Oct 2020 14:12:40 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei Subject: [PATCH v2 10/10] dt-bindings: arm: hisilicon: add missing properties into cpuctrl.yaml Date: Mon, 12 Oct 2020 14:12:25 +0800 Message-ID: <20201012061225.1597-11-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20201012061225.1597-1-thunder.leizhen@huawei.com> References: <20201012061225.1597-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.134] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add properties: #address-cells, #size-cells and ranges. Due to the Hisilicon CPU controller node may contains child nodes, change the value of "additionalProperties" from "false" to "type: object". The corresponding examples are also added. Signed-off-by: Zhen Lei --- .../bindings/arm/hisilicon/controller/cpuctrl.yaml | 27 +++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml index f6a314db3a59416..528dad4cde3cd19 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml @@ -21,9 +21,34 @@ properties: reg: maxItems: 1 + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + required: - compatible - reg -additionalProperties: false +additionalProperties: + type: object + +examples: + - | + cpuctrl@a22000 { + compatible = "hisilicon,cpuctrl"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x00a22000 0x2000>; + ranges = <0 0x00a22000 0x2000>; + + clock: clock@0 { + compatible = "hisilicon,hix5hd2-clock"; + reg = <0 0x2000>; + #clock-cells = <1>; + }; + }; ...