From patchwork Mon Oct 5 09:31:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 314056 Delivered-To: patch@linaro.org Received: by 2002:a92:d603:0:0:0:0:0 with SMTP id w3csp1138874ilm; Mon, 5 Oct 2020 02:32:35 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxspn6K0bWk7bbalfJbkGzZrkNhjQVxmVwG/l+w2FgrVvKHNMYN9HR1rM1Y+ApYl+zUzWdG X-Received: by 2002:a05:6402:10c7:: with SMTP id p7mr16279098edu.34.1601890355019; Mon, 05 Oct 2020 02:32:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601890355; cv=none; d=google.com; s=arc-20160816; b=lAdzF4UFq5k1qkPpDoXYQfAzdz85xOFe50ItxhdRKTUzxtO6wmysdxOKNVxy7o9DdZ PgitxMmZJeLvBJbpWxCzWiEAlP3pJjJrDu1qIYKemQRJX89hcAwS6vyQn4M9cJmkHFN3 nzFd89m3g/XQMqxltl4d235QFyo0iZiLKpotwRGc3EqVM6YqyyVGdKIaXIT4QyjwfHW5 HVFod1XXvgXfV5E4+dgteFpGPb0cUNMwIjFXPpfe3Sq03k0Y4SrfiHrZp51npvQHISa8 pUEX8kdJYz4f8sj/ZLU/dt+EPQSQNZ1SBN5QXsalDn07YlaJ0JI7aocrWd3lmVTLL796 UYDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=0ChHcHi6Ji1r+llty/7EuPk/EuojfII4VV6B3JIzI5g=; b=Um3Ty4l+tZEIc0WuY7KtA/FiX2d0juj+jMzS7AIkkuSM8WuxpMMVTrD+kP9fCLC5A0 q2fzIZvYnz/NwHXxHcveqyOQpxlcMuxMYN7j82zgA5RnLVsi6ZGdeewP2JprLhIwisl6 FNyznWZOBNymvNJRsGXng01LJqNsIp9vwE730FGi66U5cYXNkhTxmwRqaMvDtTjaG+2t 9KVLghViI40UyLzHZ2Agm0R7wetEcMjIaFrGLfmg5+jF3Xd0Dfx+OC5yRVqTK6iaHHib s7jE8z8jhZWt/ggVqkbIFVUKDPuZtHlmlgD3WORg4jg044zbbUyTUNsPP5FGSm3DfQru S40w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IMmJFZlZ; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id a12si6881678ejs.60.2020.10.05.02.32.34; Mon, 05 Oct 2020 02:32:35 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IMmJFZlZ; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726320AbgJEJce (ORCPT + 6 others); Mon, 5 Oct 2020 05:32:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726267AbgJEJca (ORCPT ); Mon, 5 Oct 2020 05:32:30 -0400 Received: from mail-pg1-x543.google.com (mail-pg1-x543.google.com [IPv6:2607:f8b0:4864:20::543]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D8C6C0613A8 for ; Mon, 5 Oct 2020 02:32:30 -0700 (PDT) Received: by mail-pg1-x543.google.com with SMTP id t14so5631034pgl.10 for ; Mon, 05 Oct 2020 02:32:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0ChHcHi6Ji1r+llty/7EuPk/EuojfII4VV6B3JIzI5g=; b=IMmJFZlZMNauoUwA97x41mJ25Tg2rWc0XRfHeKKxD2uCdoGfQJRHvMJuU7TR/qKP+a rtRSEXn8GCK/oZKn/mFkrlX5pwa1yJd4cBxiMJ/f5Mg3pdasJ1HUrvUoxab1rOVQW7f+ Sv82vprlPG5lUew3vgriaoBsWKXBF8UV/jWrNR42C943l7VrinnNPCaW8OMcheyWr4eV MhE3L8cnNwm42ETC5ipAwrAYHtsTB9Cs1uXZOhJk1GQEbKcsqpSyybgEJZ7tUOHhC73O IGI1lPu0mPAKbdyEIzd+bOBtt2ZRmL2y2PNMGW6TWMH6fYh9NUfycAoQPdgRNKxOPaJH E4lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0ChHcHi6Ji1r+llty/7EuPk/EuojfII4VV6B3JIzI5g=; b=lj4s6+c671fw+ptc6jGUCc75OIXdQaex6f0mSFxMfzNDzHEu1LKor9R4Nuo4yY7jC1 4oqZ+4xCOVmKLai8BkYMEGVYF8kuiNgEX3oMzXJZOw/hpDjsel2w/TlZ7k5aQcOh0VFv x+acUybrhe5kROQ24fZ4x15tFYNt5spKQEt4CVzanLaWbaCn/A4QwxwoHoa4Bct0haU6 EvEvXm/+z026HWUZpNv3pdMqppo37cktBVlKjrdUDJFARRAumpdtyjJdWet0uomLcrMr bE9RTtWmaRdvJDPNH+vq2gh4HV8YhyMdZ4/6nhdXkHRmrk0qzHPLGJlBxdb4iAoAY/7J quqA== X-Gm-Message-State: AOAM533dj0nK/XflFgiDDeEVS3ezMG9KhYRRn8y+c+1c5XyuHZVhKIP0 uKh0CEQ329pag5DLqiDdSe24 X-Received: by 2002:a65:6685:: with SMTP id b5mr13769766pgw.385.1601890349715; Mon, 05 Oct 2020 02:32:29 -0700 (PDT) Received: from localhost.localdomain ([103.59.133.81]) by smtp.googlemail.com with ESMTPSA id 124sm11298894pfd.132.2020.10.05.02.32.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Oct 2020 02:32:29 -0700 (PDT) From: Manivannan Sadhasivam To: agross@kernel.org, bjorn.andersson@linaro.org, kishon@ti.com, vkoul@kernel.org, robh@kernel.org Cc: svarbanov@mm-sol.com, bhelgaas@google.com, lorenzo.pieralisi@arm.com, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, mgautam@codeaurora.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v4 3/5] dt-bindings: pci: qcom: Document PCIe bindings for SM8250 SoC Date: Mon, 5 Oct 2020 15:01:50 +0530 Message-Id: <20201005093152.13489-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201005093152.13489-1-manivannan.sadhasivam@linaro.org> References: <20201005093152.13489-1-manivannan.sadhasivam@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the PCIe DT bindings for SM8250 SoC. The PCIe IP is similar to the one used on SDM845, hence just add the compatible along with the optional "atu" register region. Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 02bc81bb8b2d..3b55310390a0 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -13,6 +13,7 @@ - "qcom,pcie-ipq8074" for ipq8074 - "qcom,pcie-qcs404" for qcs404 - "qcom,pcie-sdm845" for sdm845 + - "qcom,pcie-sm8250" for sm8250 - reg: Usage: required @@ -27,6 +28,7 @@ - "dbi" DesignWare PCIe registers - "elbi" External local bus interface registers - "config" PCIe configuration space + - "atu" ATU address space (optional) - device_type: Usage: required @@ -131,7 +133,7 @@ - "slave_bus" AXI Slave clock -clock-names: - Usage: required for sdm845 + Usage: required for sdm845 and sm8250 Value type: Definition: Should contain the following entries - "aux" Auxiliary clock @@ -206,7 +208,7 @@ - "ahb" AHB reset - reset-names: - Usage: required for sdm845 + Usage: required for sdm845 and sm8250 Value type: Definition: Should contain the following entries - "pci" PCIe core reset