From patchwork Wed Sep 30 07:45:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 313846 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4806773ilg; Wed, 30 Sep 2020 00:46:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwkGG5K5+KEjaBgRBSuWrkziL8+L6zlIj63wx6pAXasFyAHMSYVQqIaSIVJTY4dGuEsGmXc X-Received: by 2002:a17:906:c447:: with SMTP id ck7mr1514117ejb.358.1601451969601; Wed, 30 Sep 2020 00:46:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601451969; cv=none; d=google.com; s=arc-20160816; b=O2n3be8Ns9EtbCVcNQB8gSVFj+IjT5jY0H1bAufMmrb9XyjlnwEwPGzNszN7qcqV8m LKEzXpoOadS35XL+tSMuzU4vpzKn+7hGF/0xcmoUFBeiVY2UMfaqi3RA/2ObSk3mnP8+ 4F+lYdm1Pk2pReH2kI+Jykny1ZD/NhG8X1nPzBHIb+xe8AbVKttJqgDja6JI8VN65OK+ p0A/qQHTKMBSbJ28vW/B+Ko3oHBAAe4yTJJrgqwJdh4W5hE3CUscK34eIIIPwm9aroo4 MKJRkGCyB+pH8V/g2J9hlELLUZqDoB6En7jbL1Vyz/kK8HEBaX6GQy5GoY3Db0KBUh8L TcEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=z4PPovzQEANzFGlTucphev3Y2X5Xdtk/9cOGjAz9NEk=; b=Iegv0DKg0krUzg3XPU8L+cu9m5mhbRugQqh5SCh//wEjqGUUyublV4OLGrGZhpAnLd QTdSkSDavSrTVxjp7uVXhMPNlRuLd6OItkn+VlfBbtTB52D3oDNNAZ+1RYEIqmC99u2X yBTgWC7FLoeFfepWpQcTb/rvW5TZbse7vIS0k98enxsIlzV5eLY7hGFXZ3Uz5mAnsWoV 26PdZVfiIFoyuYX6ELpCoQL2vPDZJMWWTG/LrmB3sVOMaIwSROYke08zaMDWqss22rpS 50Cf+rwWNdtg6HITYhfr+f1UlY0XdpEAa+oyxRKH2eLlXlVrHz8jD8aEX0A5Uu189Fug lntg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=nKuqftBW; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id n17si447164edq.422.2020.09.30.00.46.09; Wed, 30 Sep 2020 00:46:09 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=nKuqftBW; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727657AbgI3HqI (ORCPT + 6 others); Wed, 30 Sep 2020 03:46:08 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:43332 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725440AbgI3HqI (ORCPT ); Wed, 30 Sep 2020 03:46:08 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 08U7jntN129950; Wed, 30 Sep 2020 02:45:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1601451949; bh=z4PPovzQEANzFGlTucphev3Y2X5Xdtk/9cOGjAz9NEk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=nKuqftBW8Wodi3LDqr3p/roFj8wLDBXD4ShGB9CazK9cp90SVb4HSgiVObq+lPCw/ pjEsRXWLj+a98xVbsROSmcu0vqKunBN7yZbnl4BrFaox2DPayBrivCHZQBazS56WMp iKxtHHIjegFKaG5e6NG7K2AZMQB4LH7lvIRgke/0= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 08U7jnGY037585 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 30 Sep 2020 02:45:49 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 30 Sep 2020 02:45:48 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 30 Sep 2020 02:45:48 -0500 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 08U7jhDm078449; Wed, 30 Sep 2020 02:45:46 -0500 From: Peter Ujfalusi To: , , , , , , , CC: , , Subject: [PATCH v2 1/2] dt-bindings: irqchip: ti, sci-inta: Update for unmapped event handling Date: Wed, 30 Sep 2020 10:45:58 +0300 Message-ID: <20200930074559.18028-2-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200930074559.18028-1-peter.ujfalusi@ti.com> References: <20200930074559.18028-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The new DMA architecture introduced with AM64 introduced new event types: unampped events. These events are mapped within INTA in contrast to other K3 devices where the events with similar function was originating from the UDMAP or ringacc. The ti,unmapped-event-sources should contain phandle array to the devices in the system (typically DMA controllers) from where the unmapped events originate. Signed-off-by: Peter Ujfalusi Reviewed-by: Rob Herring --- .../bindings/interrupt-controller/ti,sci-inta.yaml | 5 +++++ 1 file changed, 5 insertions(+) -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml index c7cd05656a3e..2837b90bbb56 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml @@ -70,6 +70,11 @@ properties: - description: | "limit" specifies the limit for translation + ti,unmapped-event-sources: + $ref: /schemas/types.yaml#definitions/phandle-array + description: + Array of phandles to DMA controllers where the unmapped events originate. + required: - compatible - reg