From patchwork Wed Sep 30 03:16:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313822 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4679556ilg; Tue, 29 Sep 2020 20:18:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwUtVHKMI/fo7o6SdAI/DkRl3lLAo2G105bN5g8QrL+Rm0r7jHY/KPoRWseCnDxUTaWmNrW X-Received: by 2002:a17:906:5812:: with SMTP id m18mr801153ejq.204.1601435927431; Tue, 29 Sep 2020 20:18:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601435927; cv=none; d=google.com; s=arc-20160816; b=H8BvcnOd9iQ+bO4wyFB59KFopoWlPf8oXo3C7hO7LIBPBs2FiX+kmJdEBJUMU4/1c5 jet2ffIJ9bd2KmRdwrj5w++wY5fa+hQ6TmqJHE6CBF3Ts+Fy0olBpvl9XZPxRiSEw329 S8imWfcrLnI6yJDNd2ZA60qeG3VtamZvUWLm9IdGJYW6hhqiVvIXk9si/j5A4AgT0TL2 47x5nFOcDKnYsY41He7M2D0j3WagtJRClF0K14bpNWZFftgbb7MVOiu1bdvK6fQMjYac +gdEeV2BPvi+fNW5tjGwoymG/3CpWAknvggcSdr4JbK4A8gmhPP3PID8Xme/+2gnCsS/ nA7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=eC6vBFcx0B8FKp7TtWRxVLZF5tfza8kVadEMd87eRTQ=; b=C37KRWGHO/CdzmEGcMqJaoz7lxQBvp+4Qb91wRNEkvcgM6pYiVGCfxZASWehN0NFM2 6QUILL9w6CqoJoVrPPCchW3VQ1JfIoWjrVXOxxljYfpfj2Dnr+5/lOwg3Vt4EXJhcvk+ NEgYPNR4yaEju+7ilRGkIZsAkwqYOifLNqoZ2CE0PSDbsGzjz2Coz+t9wlRs5MBjBlxE 8iVcNlL42Q/lCbQmkRrfY00pCldoNtNW25VrtesP0lUaZsr8g+L2nv8bfzRfYU2uUdkb hUt5WR2kw99cjL2Wg68274gdbve59z88Q/TMQT7SUY6YeYkudLCKozkoGp+ebROqFMEU 398w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id dk26si176817edb.60.2020.09.29.20.18.47; Tue, 29 Sep 2020 20:18:47 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729954AbgI3DSq (ORCPT + 6 others); Tue, 29 Sep 2020 23:18:46 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:14734 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726327AbgI3DSk (ORCPT ); Tue, 29 Sep 2020 23:18:40 -0400 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 68C58BF68D4427185DE4; Wed, 30 Sep 2020 11:18:37 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.487.0; Wed, 30 Sep 2020 11:18:29 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v6 02/17] dt-bindings: arm: hisilicon: delete the descriptions of HiP05/HiP06 controllers Date: Wed, 30 Sep 2020 11:16:57 +0800 Message-ID: <20200930031712.2365-3-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200930031712.2365-1-thunder.leizhen@huawei.com> References: <20200930031712.2365-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The compatible strings of Hi6220 SRAM controller, HiP05/HiP06 PCIe-SAS subsystem controller, HiP05/HiP06 PERI subsystem controller and HiP05/HiP06 DSA subsystem controller is in syscon.yaml now. Signed-off-by: Zhen Lei --- .../bindings/arm/hisilicon/hisilicon.txt | 68 ---------------------- 1 file changed, 68 deletions(-) -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index a97f643e7d1c760..54f423d87a80a6a 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -186,24 +186,6 @@ Example: #clock-cells = <1>; }; - -Hisilicon Hi6220 SRAM controller - -Required properties: -- compatible : "hisilicon,hi6220-sramctrl", "syscon" -- reg : Register address and size - -Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several -SRAM banks for power management, modem, security, etc. Further, use "syscon" -managing the common sram which can be shared by multiple modules. - -Example: - /*for Hi6220*/ - sram: sram@fff80000 { - compatible = "hisilicon,hi6220-sramctrl", "syscon"; - reg = <0x0 0xfff80000 0x0 0x12000>; - }; - ----------------------------------------------------------------------- Hisilicon HiP01 system controller @@ -226,56 +208,6 @@ Example: }; ----------------------------------------------------------------------- -Hisilicon HiP05/HiP06 PCIe-SAS sub system controller - -Required properties: -- compatible : "hisilicon,pcie-sas-subctrl", "syscon"; -- reg : Register address and size - -The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in -HiP05 or HiP06 Soc to implement some basic configurations. - -Example: - /* for HiP05 PCIe-SAS sub system */ - pcie_sas: system_controller@b0000000 { - compatible = "hisilicon,pcie-sas-subctrl", "syscon"; - reg = <0xb0000000 0x10000>; - }; - -Hisilicon HiP05/HiP06 PERI sub system controller - -Required properties: -- compatible : "hisilicon,peri-subctrl", "syscon"; -- reg : Register address and size - -The PERI sub system controller is shared by peripheral controllers in -HiP05 or HiP06 Soc to implement some basic configurations. The peripheral -controllers include mdio, ddr, iic, uart, timer and so on. - -Example: - /* for HiP05 sub peri system */ - peri_c_subctrl: syscon@80000000 { - compatible = "hisilicon,peri-subctrl", "syscon"; - reg = <0x0 0x80000000 0x0 0x10000>; - }; - -Hisilicon HiP05/HiP06 DSA sub system controller - -Required properties: -- compatible : "hisilicon,dsa-subctrl", "syscon"; -- reg : Register address and size - -The DSA sub system controller is shared by peripheral controllers in -HiP05 or HiP06 Soc to implement some basic configurations. - -Example: - /* for HiP05 dsa sub system */ - pcie_sas: system_controller@a0000000 { - compatible = "hisilicon,dsa-subctrl", "syscon"; - reg = <0xa0000000 0x10000>; - }; - ------------------------------------------------------------------------ Hisilicon CPU controller Required properties: