From patchwork Wed Sep 30 03:17:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313826 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4679662ilg; Tue, 29 Sep 2020 20:19:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz199h3Uh6Ouk6YsctNmBVXEW1NjyZ2mjiz5Lu6BXlL0i7XRwmxsWGV9uQA1PJ44edHwv3o X-Received: by 2002:a17:906:b2ce:: with SMTP id cf14mr742049ejb.352.1601435946121; Tue, 29 Sep 2020 20:19:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601435946; cv=none; d=google.com; s=arc-20160816; b=wXQFiavq6WKc0r/dsmMOScj7BsekptcJA+4sqNCecr+umzy/oXEPBuEggLaEPBSuXr +129d8saoyqmZ6a9dNvdgMMckDXVaXtDuUkirPXJa3vVOyXgFdvh8XiUabZT6vLrVX18 QpPS+Q7oT4WFbnImDhG6goxoOox95jcD5tAtkcr8BG8IUm92LIDdgjUUcfdPYeGaSXFc EnTIqEKwOmAW7wHa0AwEMq/7ozgSK7BmHlA8zkeRZfh8kVq5a19pUs9yXnCCS3zf/Zmp WPpmHXWZDffUoAHmuBpbusn2ZIAqk1rOYiLdtXByH4UH4W7dgGKOb7hiH3u8tpzJ1wr+ kBxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=AhY/l5zX8CGyId+U6a4msgWxrG/jfEsl6SmbEzBYbAU=; b=kpYBt2yUmhkjD0JPS/Hv5JRDhP7pZhBO8sxzmEYF27hGQ7EZqvWQshQMyVMhOHFD96 /MeUOqFA0jwcI/5EdXUjhpW2d4dXjJJRaniXGvgEoG31wFifjUhXoM31sqnggB8463KJ SzAoPTI3faX+KO4IoxfNWYW0lF/aaQK9SaXObo8WtZZ7H/vmmQ5sxjwgkUlShoj81UTX /orfE1nau3Prvp7cpZG565GXiL2P9cSyxIP0WsrYU6mLByC8aSM6xnfFE9qT7640QfDV 3r1HvYhmvjfp0LOYEgHSIOFUTFJOKsz4uRaSKlIEU1cV0YfcT4B7NbcrG3z/exSP8YD6 A46g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id y7si182423edw.23.2020.09.29.20.19.05; Tue, 29 Sep 2020 20:19:06 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730044AbgI3DTF (ORCPT + 6 others); Tue, 29 Sep 2020 23:19:05 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:14740 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729973AbgI3DSt (ORCPT ); Tue, 29 Sep 2020 23:18:49 -0400 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id B36B3205B953FF83444C; Wed, 30 Sep 2020 11:18:47 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.487.0; Wed, 30 Sep 2020 11:18:38 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v6 17/17] dt-bindings: arm: hisilicon: convert LPC controller bindings to json-schema Date: Wed, 30 Sep 2020 11:17:12 +0800 Message-ID: <20200930031712.2365-18-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200930031712.2365-1-thunder.leizhen@huawei.com> References: <20200930031712.2365-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../arm/hisilicon/hisilicon-low-pin-count.txt | 33 ------------ .../bindings/arm/hisilicon/low-pin-count.yaml | 61 ++++++++++++++++++++++ 2 files changed, 61 insertions(+), 33 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/low-pin-count.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt deleted file mode 100644 index 10bd35f9207f2ee..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt +++ /dev/null @@ -1,33 +0,0 @@ -Hisilicon Hip06 Low Pin Count device - Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which - provides I/O access to some legacy ISA devices. - Hip06 is based on arm64 architecture where there is no I/O space. So, the - I/O ports here are not CPU addresses, and there is no 'ranges' property in - LPC device node. - -Required properties: -- compatible: value should be as follows: - (a) "hisilicon,hip06-lpc" - (b) "hisilicon,hip07-lpc" -- #address-cells: must be 2 which stick to the ISA/EISA binding doc. -- #size-cells: must be 1 which stick to the ISA/EISA binding doc. -- reg: base memory range where the LPC register set is mapped. - -Note: - The node name before '@' must be "isa" to represent the binding stick to the - ISA/EISA binding specification. - -Example: - -isa@a01b0000 { - compatible = "hisilicon,hip06-lpc"; - #address-cells = <2>; - #size-cells = <1>; - reg = <0x0 0xa01b0000 0x0 0x1000>; - - ipmi0: bt@e4 { - compatible = "ipmi-bt"; - device_type = "ipmi"; - reg = <0x01 0xe4 0x04>; - }; -}; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/low-pin-count.yaml b/Documentation/devicetree/bindings/arm/hisilicon/low-pin-count.yaml new file mode 100644 index 000000000000000..3b36e683bb1511d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/low-pin-count.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/low-pin-count.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon HiP06 Low Pin Count device + +maintainers: + - Wei Xu + +description: | + Hisilicon HiP06 SoCs implement a Low Pin Count (LPC) controller, which + provides I/O access to some legacy ISA devices. + HiP06 is based on arm64 architecture where there is no I/O space. So, the + I/O ports here are not CPU addresses, and there is no 'ranges' property in + LPC device node. + +properties: + $nodename: + pattern: '^isa@[0-9a-f]+$' + description: | + The node name before '@' must be "isa" to represent the binding stick + to the ISA/EISA binding specification. + + compatible: + enum: + - hisilicon,hip06-lpc + - hisilicon,hip07-lpc + + reg: + maxItems: 1 + + '#address-cells': + const: 2 + + '#size-cells': + const: 1 + +required: + - compatible + - reg + +additionalProperties: + type: object + +examples: + - | + isa@a01b0000 { + compatible = "hisilicon,hip06-lpc"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0xa01b0000 0x1000>; + + ipmi0: bt@e4 { + compatible = "ipmi-bt"; + device_type = "ipmi"; + reg = <0x01 0xe4 0x04>; + }; + }; +...