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[23.128.96.18]) by mx.google.com with ESMTP id v10si305218ejf.80.2020.09.29.20.18.54; Tue, 29 Sep 2020 20:18:54 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729992AbgI3DSx (ORCPT + 6 others); Tue, 29 Sep 2020 23:18:53 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:53798 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729945AbgI3DSo (ORCPT ); Tue, 29 Sep 2020 23:18:44 -0400 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id A0F9A8FB9F7044AB98F9; Wed, 30 Sep 2020 11:18:42 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.487.0; Wed, 30 Sep 2020 11:18:35 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v6 11/17] dt-bindings: arm: hisilicon: convert hisilicon, cpuctrl bindings to json-schema Date: Wed, 30 Sep 2020 11:17:06 +0800 Message-ID: <20200930031712.2365-12-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200930031712.2365-1-thunder.leizhen@huawei.com> References: <20200930031712.2365-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon CPU controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../bindings/arm/hisilicon/controller/cpuctrl.yaml | 29 ++++++++++++++++++++++ .../arm/hisilicon/controller/hisilicon,cpuctrl.txt | 8 ------ 2 files changed, 29 insertions(+), 8 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml new file mode 100644 index 000000000000000..f6a314db3a59416 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/cpuctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon CPU controller + +maintainers: + - Wei Xu + +description: | + The clock registers and power registers of secondary cores are defined + in CPU controller, especially in HIX5HD2 SoC. + +properties: + compatible: + items: + - const: hisilicon,cpuctrl + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false +... diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt deleted file mode 100644 index ceffac537671668..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt +++ /dev/null @@ -1,8 +0,0 @@ -Hisilicon CPU controller - -Required properties: -- compatible : "hisilicon,cpuctrl" -- reg : Register address and size - -The clock registers and power registers of secondary cores are defined -in CPU controller, especially in HIX5HD2 SoC.