From patchwork Tue Sep 29 14:14:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313762 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4206449ilg; Tue, 29 Sep 2020 07:15:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxRQcKJZ2r2RqGMEw7Qqd/uEVNFAYgt31IZgioJzQTk7RstCYrX5qfFUYPq2lFZhQY29Ob4 X-Received: by 2002:a17:906:4cc2:: with SMTP id q2mr4293912ejt.422.1601388952354; Tue, 29 Sep 2020 07:15:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601388952; cv=none; d=google.com; s=arc-20160816; b=znyExwAlMTvYZAL6EvsZKfl9Vcsri105tDZ5bwV4jt8M6OkAqyh+3deGSrwopIS8la wkWBNNgBuw7NnAT3Qbh7ReqLj+87I5for7AaXRORVQivd2ZqDnhSyobFHNHGWWhzeHtW QP3129+fi4+ERLiy87KeoEL6KIB+InFs+F77lXJwCNJ3wLR0Lc4V32JvpITxV+PKq9lS AdZkfdJTzhCibMhlr6ZYVw7y5q5lSvHjYE/fCWo7IPU+vyideu7I7A6dEIFwrKRVpktH kUoX/mwDP7xn7eUrnks12tkicB2IyC4rgyRtC3CnaoKau4AOYMJnlanqdIAFU2eL2sqs pK5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=AhY/l5zX8CGyId+U6a4msgWxrG/jfEsl6SmbEzBYbAU=; b=0B7jYkU0Plx1tYqykDgEcpvz1Wog869WpV3u7dg2laEJc0GKrIi0XtwFqO8re73mdU Drc8t3o5e1E0uvmQXZKm0dK+54wjFShnLkjpJyGPa0yzBcorTV8OCNT2teCp1YIpGLjq 1GhrRV1WvuOk/ZIESJPov/vPB5nkCpIiQvS4qx9cuH3CLEubP7lg/rB/+mGBBijJtKvJ kEtSRA0k58GCuANeY6NRSBSC8dfnvxomrAwcNWeur7K+mUib7ISSZC+3rCguoQVlSk63 pfFgHCN5AR/Tss+ysDSBiv7yc02ut0MfGwcaLl6+U3ibb1A5RTnhhLy130clOuhCiU0j Qx9g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id bt13si2973506ejb.259.2020.09.29.07.15.52; Tue, 29 Sep 2020 07:15:52 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731115AbgI2OPh (ORCPT + 6 others); Tue, 29 Sep 2020 10:15:37 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:39006 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1731045AbgI2OPf (ORCPT ); Tue, 29 Sep 2020 10:15:35 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 8CE88B5C14036196774B; Tue, 29 Sep 2020 22:15:29 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Tue, 29 Sep 2020 22:15:20 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v5 17/17] dt-bindings: arm: hisilicon: convert LPC controller bindings to json-schema Date: Tue, 29 Sep 2020 22:14:54 +0800 Message-ID: <20200929141454.2312-18-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200929141454.2312-1-thunder.leizhen@huawei.com> References: <20200929141454.2312-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../arm/hisilicon/hisilicon-low-pin-count.txt | 33 ------------ .../bindings/arm/hisilicon/low-pin-count.yaml | 61 ++++++++++++++++++++++ 2 files changed, 61 insertions(+), 33 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/low-pin-count.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt deleted file mode 100644 index 10bd35f9207f2ee..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt +++ /dev/null @@ -1,33 +0,0 @@ -Hisilicon Hip06 Low Pin Count device - Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which - provides I/O access to some legacy ISA devices. - Hip06 is based on arm64 architecture where there is no I/O space. So, the - I/O ports here are not CPU addresses, and there is no 'ranges' property in - LPC device node. - -Required properties: -- compatible: value should be as follows: - (a) "hisilicon,hip06-lpc" - (b) "hisilicon,hip07-lpc" -- #address-cells: must be 2 which stick to the ISA/EISA binding doc. -- #size-cells: must be 1 which stick to the ISA/EISA binding doc. -- reg: base memory range where the LPC register set is mapped. - -Note: - The node name before '@' must be "isa" to represent the binding stick to the - ISA/EISA binding specification. - -Example: - -isa@a01b0000 { - compatible = "hisilicon,hip06-lpc"; - #address-cells = <2>; - #size-cells = <1>; - reg = <0x0 0xa01b0000 0x0 0x1000>; - - ipmi0: bt@e4 { - compatible = "ipmi-bt"; - device_type = "ipmi"; - reg = <0x01 0xe4 0x04>; - }; -}; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/low-pin-count.yaml b/Documentation/devicetree/bindings/arm/hisilicon/low-pin-count.yaml new file mode 100644 index 000000000000000..3b36e683bb1511d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/low-pin-count.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/low-pin-count.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon HiP06 Low Pin Count device + +maintainers: + - Wei Xu + +description: | + Hisilicon HiP06 SoCs implement a Low Pin Count (LPC) controller, which + provides I/O access to some legacy ISA devices. + HiP06 is based on arm64 architecture where there is no I/O space. So, the + I/O ports here are not CPU addresses, and there is no 'ranges' property in + LPC device node. + +properties: + $nodename: + pattern: '^isa@[0-9a-f]+$' + description: | + The node name before '@' must be "isa" to represent the binding stick + to the ISA/EISA binding specification. + + compatible: + enum: + - hisilicon,hip06-lpc + - hisilicon,hip07-lpc + + reg: + maxItems: 1 + + '#address-cells': + const: 2 + + '#size-cells': + const: 1 + +required: + - compatible + - reg + +additionalProperties: + type: object + +examples: + - | + isa@a01b0000 { + compatible = "hisilicon,hip06-lpc"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0xa01b0000 0x1000>; + + ipmi0: bt@e4 { + compatible = "ipmi-bt"; + device_type = "ipmi"; + reg = <0x01 0xe4 0x04>; + }; + }; +...