From patchwork Tue Sep 29 02:48:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 313698 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp3788708ilg; Mon, 28 Sep 2020 19:48:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzY5rsoX6TSMHFAcInFOt34FTFM1e1HRyQBaNsb9bTWnfJ7jSTVbw5gO2XRkjQpdevyc/VU X-Received: by 2002:a50:fc87:: with SMTP id f7mr997181edq.162.1601347720490; Mon, 28 Sep 2020 19:48:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601347720; cv=none; d=google.com; s=arc-20160816; b=mdxcNSsiHKMKQI2uGG9R6nEVvYApdv/aFH3Cj21Oz2263WCPgI3EAIzVpIfrvXFlLl VdX+TJIq3cSIyAgfqKVMkngcN14/72osXHqECj7FCEgVqbwlOJcIv0u78al/gXkF5YA8 1tNq+7hDPUn1CEzSeDUDvHfvYAd6TMwMsqg/0zhI83J6mZK0YXJcqT68m9XWbp5fY1BI C2VtsFB9lWPvkKjewfjZVnwUMe4qMMqTiTtzzeXpGSyrWEykRVu3o70ODo+daNYAMXek 7RFtpeZ04fVKbKUVIj943fKRJ4R6HjHxgtmx373XvSAPAHTYz0VI3PbXcwfLjEoW/n2c PCXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=MYjOnjkGIVKHMQGYGN9yEl1//k6QScW5VXq5KSd4b3M=; b=f/Lbkzp6bbn1nGoTxDaVXZiTNv4UrSEM3vcLOq+Uxu7j2Q7xaLxLn2y6hd74xbenj0 uKxRj3xwIJ8kN9zfa5Rk2OjLj/9QACra/b1Qsri4P1hWuiOSgE62rhR4fmiHho4mYE9E yQo3pRN4k1I077MiNhUF0zKEGTKVIH03Ipk089KaFAYADcWaj9OIesgKMrpFb3bEYi7N qUBtCBo1cOsSK240HcNSLN28Lqv3h8Xsmad6YYP7vzf4hAdxZfyi38iPcYer7b4hy66Q SB6VqlsX3VjJEhf1CRbc0GAsQEHiE1JQMdnqfWzkN+5lDkVKOACa3Ww2mJlLapUQ17rp Sfbw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id ng5si1796021ejb.532.2020.09.28.19.48.40; Mon, 28 Sep 2020 19:48:40 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727219AbgI2Csa (ORCPT + 6 others); Mon, 28 Sep 2020 22:48:30 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:38458 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727077AbgI2Csa (ORCPT ); Mon, 28 Sep 2020 22:48:30 -0400 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 5E1701F0C5F7CC97D426; Tue, 29 Sep 2020 10:48:28 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.487.0; Tue, 29 Sep 2020 10:48:21 +0800 From: Zhen Lei To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , devicetree , linux-kernel CC: Zhen Lei , Sebastian Hesselbarth , Libin , "Kefeng Wang" Subject: [PATCH v6 1/1] dt-bindings: dw-apb-ictl: convert to json-schema Date: Tue, 29 Sep 2020 10:48:11 +0800 Message-ID: <20200929024811.2245-2-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200929024811.2245-1-thunder.leizhen@huawei.com> References: <20200929024811.2245-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Synopsys DesignWare APB interrupt controller (dw_apb_ictl) binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../interrupt-controller/snps,dw-apb-ictl.txt | 43 -------------- .../interrupt-controller/snps,dw-apb-ictl.yaml | 68 ++++++++++++++++++++++ 2 files changed, 68 insertions(+), 43 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.yaml -- 1.8.3 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt deleted file mode 100644 index 2db59df9408f4c6..000000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt +++ /dev/null @@ -1,43 +0,0 @@ -Synopsys DesignWare APB interrupt controller (dw_apb_ictl) - -Synopsys DesignWare provides interrupt controller IP for APB known as -dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with -APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt -controller in some SoCs, e.g. Hisilicon SD5203. - -Required properties: -- compatible: shall be "snps,dw-apb-ictl" -- reg: physical base address of the controller and length of memory mapped - region starting with ENABLE_LOW register -- interrupt-controller: identifies the node as an interrupt controller -- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1 - -Additional required property when it's used as secondary interrupt controller: -- interrupts: interrupt reference to primary interrupt controller - -The interrupt sources map to the corresponding bits in the interrupt -registers, i.e. -- 0 maps to bit 0 of low interrupts, -- 1 maps to bit 1 of low interrupts, -- 32 maps to bit 0 of high interrupts, -- 33 maps to bit 1 of high interrupts, -- (optional) fast interrupts start at 64. - -Example: - /* dw_apb_ictl is used as secondary interrupt controller */ - aic: interrupt-controller@3000 { - compatible = "snps,dw-apb-ictl"; - reg = <0x3000 0xc00>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - - /* dw_apb_ictl is used as primary interrupt controller */ - vic: interrupt-controller@10130000 { - compatible = "snps,dw-apb-ictl"; - reg = <0x10130000 0x1000>; - interrupt-controller; - #interrupt-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.yaml b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.yaml new file mode 100644 index 000000000000000..33b3992d1c27c63 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/snps,dw-apb-ictl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare APB interrupt controller (dw_apb_ictl) + +maintainers: + - Sebastian Hesselbarth + +description: | + Synopsys DesignWare provides interrupt controller IP for APB known as + dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs + with APB bus, e.g. Marvell Armada 1500. It can also be used as primary + interrupt controller in some SoCs, e.g. Hisilicon SD5203. + + The interrupt sources map to the corresponding bits in the interrupt + registers, i.e. + - 0 maps to bit 0 of low interrupts, + - 1 maps to bit 1 of low interrupts, + - 32 maps to bit 0 of high interrupts, + - 33 maps to bit 1 of high interrupts, + - (optional) fast interrupts start at 64. + +properties: + compatible: + const: snps,dw-apb-ictl + + interrupt-controller: true + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#interrupt-cells": + const: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + /* dw_apb_ictl is used as secondary interrupt controller */ + interrupt-controller@3000 { + compatible = "snps,dw-apb-ictl"; + reg = <0x3000 0xc00>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <0 3 4>; + }; + + /* dw_apb_ictl is used as primary interrupt controller */ + interrupt-controller@10130000 { + compatible = "snps,dw-apb-ictl"; + reg = <0x10130000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + }; +...