From patchwork Sun Sep 27 06:21:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313595 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2398330ilg; Sat, 26 Sep 2020 23:28:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxKE5lC9gtLYrnVHC2TbN9qfp3UwC3hlDDtBSMD+19LBjtgd45Lmotz12pVS7I37weHXZLZ X-Received: by 2002:a50:e3c4:: with SMTP id c4mr10011747edm.90.1601188091211; Sat, 26 Sep 2020 23:28:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601188091; cv=none; d=google.com; s=arc-20160816; b=crJ8jdMTF4j6LECn2yCJLCr5QT5DIgxKPV2PyMqjeehtHiMnrkxbQB8mVX9RSVpiVo IhhomtebqMMKSbsrWKWf65DrZcJNZ/QwGEfs8ZkEk20A2CfzL7IamH2313/Yehh7gN1M eYgRTakEyb4H8h6l/bMcju+FBbxqN2Yihl4PsD4xxwWbKjW5V7rRphxESeDyeQz4Z7zY S/iyY4NmyI5Dtsa9b6w5V/uCx9yFGW9/4vNTV8kQPkq2zamomFq4mJ2wQIssNkBpXruD XS/0WQmWA/rKJdrRkarDkew/BNmZJokk5V/+N9TYJPKeB7GiGLjUKdKpvCQQHBQx4e5X JdTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=7S2NxD+MhlhEdXZBEzBKVlIncr3e0pL4ulB33Jw88Vg=; b=GOpkgCGj6yEM9GY0a2Bnfbpm9tgx5BV27FSyfpNEOr2G8yb60pU3r1Pp2zyKadslaS ZxP6J2xcM9PR/N1RBScaXRwE5pAiN7ueCTk/C9+CoKspcDaCnF98MKfISdlkLQOOQrzC 7yJmVrWC9VOe3rx1PICw9HYoKvsiASrDX+cSCfJuYlMZG4BMmufqyY+qj8QThmMR4v2N YQu+GedBMuWlKKCE3kcPkTbRJv6mjpl7WyckPQJRG/AJZm1msqq4DQiQYfSrl+P3G5sk 756YnVAEw5NxquX/ekFWjcCUSdukdmbhIBNXP4wplMigprw5+Wq6TGfdnXXEZUzTMROm pp5A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id a10si4787191ejy.454.2020.09.26.23.28.11; Sat, 26 Sep 2020 23:28:11 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730562AbgI0G2K (ORCPT + 6 others); Sun, 27 Sep 2020 02:28:10 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14294 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730372AbgI0G06 (ORCPT ); Sun, 27 Sep 2020 02:26:58 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id CEC84D0412295B5696DD; Sun, 27 Sep 2020 14:26:52 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Sun, 27 Sep 2020 14:26:44 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v3 05/21] ARM: hisi: add support for SD5203 SoC Date: Sun, 27 Sep 2020 14:21:13 +0800 Message-ID: <20200927062129.4573-6-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200927062129.4573-1-thunder.leizhen@huawei.com> References: <20200927062129.4573-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Kefeng Wang Enable support for the Hisilicon SD5203 SoC. The core is ARM926EJ-S. Signed-off-by: Kefeng Wang Signed-off-by: Zhen Lei --- arch/arm/mach-hisi/Kconfig | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) -- 1.8.3 diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig index 3b010fe7c0e9b48..2e980f834a6aa1b 100644 --- a/arch/arm/mach-hisi/Kconfig +++ b/arch/arm/mach-hisi/Kconfig @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-only config ARCH_HISI bool "Hisilicon SoC Support" - depends on ARCH_MULTI_V7 + depends on ARCH_MULTI_V7 || ARCH_MULTI_V5 select ARM_AMBA - select ARM_GIC + select ARM_GIC if ARCH_MULTI_V7 select ARM_TIMER_SP804 select POWER_RESET select POWER_RESET_HISI @@ -15,6 +15,7 @@ menu "Hisilicon platform type" config ARCH_HI3xxx bool "Hisilicon Hi36xx family" + depends on ARCH_MULTI_V7 select CACHE_L2X0 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP @@ -25,6 +26,7 @@ config ARCH_HI3xxx config ARCH_HIP01 bool "Hisilicon HIP01 family" + depends on ARCH_MULTI_V7 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select ARM_GLOBAL_TIMER @@ -33,6 +35,7 @@ config ARCH_HIP01 config ARCH_HIP04 bool "Hisilicon HiP04 Cortex A15 family" + depends on ARCH_MULTI_V7 select ARM_ERRATA_798181 if SMP select HAVE_ARM_ARCH_TIMER select MCPM if SMP @@ -43,6 +46,7 @@ config ARCH_HIP04 config ARCH_HIX5HD2 bool "Hisilicon X5HD2 family" + depends on ARCH_MULTI_V7 select CACHE_L2X0 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP @@ -50,6 +54,14 @@ config ARCH_HIX5HD2 select PINCTRL_SINGLE help Support for Hisilicon HIX5HD2 SoC family + +config ARCH_SD5203 + bool "Hisilicon SD5203 family" + depends on ARCH_MULTI_V5 + select DW_APB_ICTL + help + Support for Hisilicon SD5203 SoC family + endmenu endif