From patchwork Sun Sep 27 06:21:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313590 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2398176ilg; Sat, 26 Sep 2020 23:27:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwnNQ7y61JlCJjb0roqxHLEmEcxrgLuVQpJu0FAjVqhgGWp8pA1ivGDVQiZsZYS9RMZwlse X-Received: by 2002:a50:d94d:: with SMTP id u13mr9424766edj.365.1601188066875; Sat, 26 Sep 2020 23:27:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601188066; cv=none; d=google.com; s=arc-20160816; b=QrR/01twn13R8bnZ+MZXSy3W+fZpkJH8TYgTPry1riJblscan1m9a3pWd5lkGuk53v PgtwzhAei5NuCxfBMvjuV1HFCfJAZjP8labAbIhzJg8L7rTlmSLBXQX+Y2QMcl81bTo6 kf8PGOT2HeoOcyZdalPbc9hJSUQfPp81WS93frMf5DiJ7O1sKkNfEb6cwUSN5DyYIHKd i0QzoyRDLaEOUmXaKN5djdP8wEkQ4JGpFHiK4gW4+0sYAbLxxqqInNJobZTBekFKnBmZ aGhqc6KEdtQ9imutRK6iwD+mWcA7JJu7jUqdVqez5AnqidBoZ+nMcM1sVyPL2oVw/rzj TGRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=bvbno9/OzuoeIRTlC3fAAvz01jlEXXaHH9DfidPALL0=; b=OEMbpHY5bVCHlW+2KWo4f7a3qvn2nybnjbkEbIMWklciStl1S1NNWfDWiSFggszcp6 rKBYAlj6pWmNOnmjfOZtgfhbcbMKqlNSNZfSX7XrsOM57ZECy1wgCEHdE9lFHhKuVGgp 2SfSnQWOrvktsUP0aMXdszF4YhnPcWPWpccBvWEaMKEFaY5cjh6TDTwwXWEabKPB33se JnqW30TLh4HhOKuJBa5Ea4gh1XSJdJYdQGOX4HtwCXyahQT+ElkZv5YlQasp9B2B5DKd MWgMEzVbW/Y0unSkjICkNX6+Jovpved/NDJrOmvxRWlXg+MaiYDWCXtUmfrqvNYUsVB0 n//A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id e25si5050492ejb.260.2020.09.26.23.27.46; Sat, 26 Sep 2020 23:27:46 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730511AbgI0G1p (ORCPT + 6 others); Sun, 27 Sep 2020 02:27:45 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14297 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730259AbgI0G1A (ORCPT ); Sun, 27 Sep 2020 02:27:00 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id B71CA7A10266CD3EECD7; Sun, 27 Sep 2020 14:26:57 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Sun, 27 Sep 2020 14:26:47 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v3 11/21] dt-bindings: arm: hisilicon: convert hisilicon, cpuctrl bindings to json-schema Date: Sun, 27 Sep 2020 14:21:19 +0800 Message-ID: <20200927062129.4573-12-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200927062129.4573-1-thunder.leizhen@huawei.com> References: <20200927062129.4573-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon CPU controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../arm/hisilicon/controller/hisilicon,cpuctrl.txt | 8 ------- .../hisilicon/controller/hisilicon,cpuctrl.yaml | 28 ++++++++++++++++++++++ 2 files changed, 28 insertions(+), 8 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt deleted file mode 100644 index 0188ec93d2df70d..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt +++ /dev/null @@ -1,8 +0,0 @@ -Hisilicon CPU controller - -Required properties: -- compatible : "hisilicon,cpuctrl" -- reg : Register address and size - -The clock registers and power registers of secondary cores are defined -in CPU controller, especially in HIX5HD2 SoC. \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.yaml new file mode 100644 index 000000000000000..6db2da3fe3352da --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.yaml @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,cpuctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon CPU controller + +maintainers: + - Wei Xu + +description: | + The clock registers and power registers of secondary cores are defined + in CPU controller, especially in HIX5HD2 SoC. + +properties: + compatible: + items: + - const: hisilicon,cpuctrl + + reg: + description: Register address and size + maxItems: 1 + +required: + - compatible + - reg +... \ No newline at end of file