From patchwork Wed Sep 23 22:09:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 313435 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp848768ilg; Wed, 23 Sep 2020 15:10:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwVZADuOemli1T6oz5Y94suDrT1Rs1F7wxW4ABSNv55aRXnWVO8qEGLUkR8xO2CuXNLu40f X-Received: by 2002:a50:9fa1:: with SMTP id c30mr1427622edf.207.1600899014699; Wed, 23 Sep 2020 15:10:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600899014; cv=none; d=google.com; s=arc-20160816; b=ZTfCw+4V/oy2Lx/g5R9mrq90IsKXPF6h0zQcKedL8IcZaioX2JEXrzSElKV+UnMaw8 CG+MXD0tV4SqmCevUKu4QgaRlLCm6LMXwaoLJWyLSUMWiCDuv++PHDJL5pN3QJckJ/Yj qe9pgw1r667K++pfl80+V+9/JiBRebkY/6zjNcUBldAxKh1kCQ6ms6y1uz8rXpE4s7N5 JbvCm4lE3Wu11fY8RhiWSzG7S5R3tpBjrpiU7iqwlF+8O9FuvFtRCT+MhvCHBN3mhtps Ht6wk/WTQwHPLfys5ts0AI7Mwq4JJiXDSlMo90exHdaUTXQErqK2FSfoVnp2TOokN9Uc 3gpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=zMPM4B2dMQw73A2K8MNlHJFwOwVnrAGVJ/8mNIZQ5dQ=; b=X2VxEiJMZOJ2odNSTmKXR8nFIRSNjjh0U1s4JHVMWJo6xGlsTkfYNoPtszDa81KkO7 vVSOfZS3OU26TtuCRRdWfy31DUT91NJiXHzsQTPsYFVU/eYqGRQb6vjjuD0Uuy3JEQUB KxCIzMkcY3aKJ2RdLRNx3qpeMzxiKO+GMoGsFcJjsjxI8SFUWYEY2f1aGleBxnt0ZSW2 Tht3CmYhziE9khY7dCxBHZVUqKKgtaruy+DU0ZvgsIc2zUpI4fWzAhGmnwlYTlyKChq7 G3ozIzaWmynFsGh7eeVEcr97rqyTnWJ/50ru9eZoRbhv6YAhEF4EWnCWmVwgkALC3CTF wW5A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=qrPefx9h; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id fx6si762921ejb.432.2020.09.23.15.10.14; Wed, 23 Sep 2020 15:10:14 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=qrPefx9h; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726718AbgIWWKO (ORCPT + 6 others); Wed, 23 Sep 2020 18:10:14 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:33894 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726199AbgIWWKN (ORCPT ); Wed, 23 Sep 2020 18:10:13 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 08NMAAnR114434; Wed, 23 Sep 2020 17:10:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1600899010; bh=zMPM4B2dMQw73A2K8MNlHJFwOwVnrAGVJ/8mNIZQ5dQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=qrPefx9hoY1Wueb1a9YLMjHsx+/KXgbynwdd3KMUuRyunpa/D+GRN3mCdybWftH75 8QkWYBbFA3jDUSYMoDDi/XqlLgVVL5V12PPcIE8EKyj2ht++3Whw0cJk0Re829L4hS t/2mHt94Is3pbJ/dffR1qsjKP2ZnJ13ZqqD93a9M= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 08NMAA9H081199 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 23 Sep 2020 17:10:10 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 23 Sep 2020 17:10:09 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 23 Sep 2020 17:10:09 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 08NMA8VM046679; Wed, 23 Sep 2020 17:10:09 -0500 From: Grygorii Strashko To: Tero Kristo , Rob Herring , Nishanth Menon CC: Peter Ujfalusi , Sekhar Nori , , , , Vignesh Raghavendra , Suman Anna , Kishon Vijay Abraham I , Grygorii Strashko Subject: [PATCH v4 4/4] arm64: dts: ti: k3-j7200-common-proc-board: add mcu cpsw nuss pinmux and phy defs Date: Thu, 24 Sep 2020 01:09:38 +0300 Message-ID: <20200923220938.30788-5-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200923220938.30788-1-grygorii.strashko@ti.com> References: <20200923220938.30788-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The TI j7200 EVM base board has TI DP83867 PHY connected to external CPSW NUSS Port 1 in rgmii-rxid mode. Hence, add pinmux and Ethernet PHY configuration for TI j7200 SoC MCU Gigabit Ethernet two ports Switch subsystem (CPSW NUSS). Signed-off-by: Grygorii Strashko --- .../dts/ti/k3-j7200-common-proc-board.dts | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index d257d23e27f5..b8000dfb791c 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "k3-j7200-som-p0.dtsi" +#include / { chosen { @@ -14,6 +15,32 @@ }; }; +&wkup_pmx0 { + mcu_cpsw_pins_default: mcu-cpsw-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ + J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ + J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ + J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ + J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ + J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ + J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ + J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ + J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ + J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ + J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */ + J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio1-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ + J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ + >; + }; +}; + &wkup_uart0 { /* Wakeup UART is used by System firmware */ status = "disabled"; @@ -63,3 +90,21 @@ /* UART not brought out */ status = "disabled"; }; + +&mcu_cpsw { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; +}; + +&davinci_mdio { + phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&phy0>; +};