From patchwork Fri Sep 18 15:38:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 313204 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp1441069ilg; Fri, 18 Sep 2020 08:39:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxhrfXD7Uf7NUXEGkd+faiAyKOf8BnlxxI/DoWIk2Ntqb8hnhGtZhQWiL7sAIg1fOFk35ng X-Received: by 2002:a17:906:770c:: with SMTP id q12mr35700110ejm.518.1600443550499; Fri, 18 Sep 2020 08:39:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600443550; cv=none; d=google.com; s=arc-20160816; b=IC9IPKOX6s5lnSSQFooQiRfq8QJ5bNrpurVEiFCk9Xa2PfOrOVatF1M5UObno9NR9c x83bGgsc/1d5xcZebqDSNd+Y4pkB3GZ0Zs5vSHViImACpR5XgHJwVpsoIp03FjOo0Dph Eifl61A4Mu6td7eGYIxAHDB/FjxBk5Z3RCag3WlMIVWniQOZhDO1ZCfsO9KpiWusTb84 M0Fvp9nDzHhFzkptuZVLMIXuelimzVOBJ+hNprW5MEx9eIdiLeA7uD2xh3oAj3Or2LE0 6nlqc1kkeIv0/q4iasEKdabhgdMWx3N5y/qyCSTkIRiP9ZrtC0DMmyHF1+RWzUDcFN54 JfWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=7XDPRqUzl+JVINgiR0D8+gFPVzJBv1P361gPvzhvl6M=; b=zuCAiOnUajDXqzCw7krIWyjkB7b8tS8DPAcPvhcvtCUCboou1mUcyb5IJluYf7hkYy g+bhVvuIXAnZTWgUjQN8MYgRU3/Sg62f9PSyiTczobhBzCku2V+Cu4Hj3CnMHrUISeZi F1UxOZFlca12SyAXcXOhlGYeUB+PdTQzuFuel14ClFryHkCvXSuy4UrtnssSD8/3TZgb qomJOhQaP+7EkcbgxscCB/VToouXvljdsTdMZs5vWtoKvuOGYo6ce25wKYzVexvqankJ RY7Zk4QQwSVYvYmbNx0yzxs580R/BSMnlKpAtRo75mB6lPtZDsgf1H8RECstwDHlSNHG MqvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=qO5WKj8V; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id r23si2422692ejs.259.2020.09.18.08.39.10; Fri, 18 Sep 2020 08:39:10 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=qO5WKj8V; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725955AbgIRPjF (ORCPT + 6 others); Fri, 18 Sep 2020 11:39:05 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:40494 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726044AbgIRPjD (ORCPT ); Fri, 18 Sep 2020 11:39:03 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 08IFcvHv011325; Fri, 18 Sep 2020 10:38:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1600443537; bh=7XDPRqUzl+JVINgiR0D8+gFPVzJBv1P361gPvzhvl6M=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=qO5WKj8VqbZ/lc9rJ4Jw7lvR4j11mJyVoxtk8AVuZiSk9TUk7szfS1KASOtSVrvPz iYLbzyxcV0FrOwRomAwh8U/XJ9kmRxnz935hi+G6VCBG91xi4chbz8lyNhPCjkQAjo HX282NG5ttuq5L37cAzrzqQegdI7ZFVujaEhpu/o= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 08IFcvoQ122262 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 18 Sep 2020 10:38:57 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 18 Sep 2020 10:38:57 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 18 Sep 2020 10:38:57 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 08IFcuB3094740; Fri, 18 Sep 2020 10:38:56 -0500 From: Grygorii Strashko To: Tero Kristo , Rob Herring , Nishanth Menon CC: Peter Ujfalusi , Sekhar Nori , , , , Vignesh Raghavendra , Suman Anna , Kishon Vijay Abraham I , Grygorii Strashko Subject: [PATCH v3 4/4] arm64: dts: ti: k3-j7200-common-proc-board: add mcu cpsw nuss pinmux and phy defs Date: Fri, 18 Sep 2020 18:38:29 +0300 Message-ID: <20200918153829.14686-5-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200918153829.14686-1-grygorii.strashko@ti.com> References: <20200918153829.14686-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The TI j7200 EVM base board has TI DP83867 PHY connected to external CPSW NUSS Port 1 in rgmii-rxid mode. Hence, add pinmux and Ethernet PHY configuration for TI j7200 SoC MCU Gigabit Ethernet two ports Switch subsystem (CPSW NUSS). Signed-off-by: Grygorii Strashko Tested-by: Kishon Vijay Abraham I --- .../dts/ti/k3-j7200-common-proc-board.dts | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index e27069317c4e..f7e6b9b5ef5f 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "k3-j7200-som-p0.dtsi" +#include / { chosen { @@ -14,6 +15,32 @@ }; }; +&wkup_pmx0 { + mcu_cpsw_pins_default: mcu-cpsw-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ + J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ + J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ + J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ + J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ + J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ + J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ + J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ + J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ + J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ + J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */ + J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio1-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ + J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ + >; + }; +}; + &wkup_uart0 { /* Wakeup UART is used by System firmware */ status = "disabled"; @@ -62,3 +89,21 @@ /* UART not brought out */ status = "disabled"; }; + +&mcu_cpsw { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; +}; + +&davinci_mdio { + phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&phy0>; +};