From patchwork Fri Sep 18 13:22:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313192 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp1333532ilg; Fri, 18 Sep 2020 06:23:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzenjc+BpWDIF0I8MbTPjH4yLgaqiLQ8quQhMkEEWCIEWh4GjKmzUvahHMr1EwTdIlEPdDn X-Received: by 2002:a17:906:f1d5:: with SMTP id gx21mr33992339ejb.165.1600435414588; Fri, 18 Sep 2020 06:23:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600435414; cv=none; d=google.com; s=arc-20160816; b=eSppM7Z8lRpNI079zHUQxCe1pKKCDO1rSrhID6kCQMAXgqyBNgnkaFaWBLT3XkMmGN pWyKQbHKD+sL9vgcIzVszw5mm7J0+azVKIWEokIed7RDiZdgpMWrFnrFbE72BGePLVj6 JCABU4CAVhTWxoL+A57CNOow6JZHb9PlrG6EbZW60XtgDgyfd6CMMBgt92fGhTnFXxWB a+LiU+B7VR/ZYGHw/6/mXzVxy9CWcDYD7mHlcdRJmxYt6gIu6QkLtQ5R+78DX/H1RBFz XjYlNXswaYF0L7+NeDHbHs9WgunjVFnQC+CdIMLT824Jgy2fdzyfrmX9qnvV7w6ezY1Z 2j6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=iS/+QKeGUcdLyaz3EkJwK8NVcNKZsgz7jbQ84l/NzmQ=; b=kuqn909YNkGbkO7gZTLjqqdZ4tOjHnxEZvG+w2DLWUqb2bo3rQc84pSW1bDihQbkMX QScDLMoytuF+gjB3SXQfjg+XMqM2e/MDTpsXxKYUnCQhZsRm76+vgqCASs8sjKUvAS7K 5tNFVKZdt6o/8GgiiQlUmMuIKGtdEJG4HXvE9rZeF1eEaf8nvW2KPuOagPOgjWsIl34d M7mby8tKU81Ehxrlki51xLYAI0b+xgmjrWHlkm/rHQHp/mKbJykJguusDph55R1b2Lg/ Nh+I7P38Fpbwn8L65/1cSwRNoEyHVNEByGgx8LLzTlYu/3yUBkBNvGzS9nPp/BbgclzX FLDA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id z1si2094545edx.584.2020.09.18.06.23.34; Fri, 18 Sep 2020 06:23:34 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726821AbgIRNXZ (ORCPT + 6 others); Fri, 18 Sep 2020 09:23:25 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:59478 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726778AbgIRNXT (ORCPT ); Fri, 18 Sep 2020 09:23:19 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 81C4D9DA680EC872A5B6; Fri, 18 Sep 2020 21:23:13 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Fri, 18 Sep 2020 21:23:03 +0800 From: Zhen Lei To: Rob Herring , devicetree , Daniel Lezcano , Thomas Gleixner , Haojian Zhuang , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang , Jianguo Chen Subject: [PATCH v3 8/9] clocksource: sp804: enable Hisilicon sp804 timer 64bit mode Date: Fri, 18 Sep 2020 21:22:36 +0800 Message-ID: <20200918132237.3552-9-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200918132237.3552-1-thunder.leizhen@huawei.com> References: <20200918132237.3552-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org A 100MHZ 32-bit timer will be wrapped up less than 43s. Although the kernel maintains a software high 32-bit count in the tick IRQ. But it's not applicable to the user mode APPs. Note: The kernel still uses the lower 32 bits of the timer. Signed-off-by: Zhen Lei --- drivers/clocksource/timer-sp.h | 6 ++++++ drivers/clocksource/timer-sp804.c | 11 +++++++++++ 2 files changed, 17 insertions(+) -- 1.8.3 diff --git a/drivers/clocksource/timer-sp.h b/drivers/clocksource/timer-sp.h index 1ab75cbed0e09e5..811f840be0e52fd 100644 --- a/drivers/clocksource/timer-sp.h +++ b/drivers/clocksource/timer-sp.h @@ -33,12 +33,15 @@ struct sp804_timer { int load; + int load_h; int value; + int value_h; int ctrl; int intclr; int ris; int mis; int bgload; + int bgload_h; int timer_base[NR_TIMERS]; int width; }; @@ -46,12 +49,15 @@ struct sp804_timer { struct sp804_clkevt { void __iomem *base; void __iomem *load; + void __iomem *load_h; void __iomem *value; + void __iomem *value_h; void __iomem *ctrl; void __iomem *intclr; void __iomem *ris; void __iomem *mis; void __iomem *bgload; + void __iomem *bgload_h; unsigned long reload; int width; }; diff --git a/drivers/clocksource/timer-sp804.c b/drivers/clocksource/timer-sp804.c index f0783d19522f048..6e8ad4a4ea3c737 100644 --- a/drivers/clocksource/timer-sp804.c +++ b/drivers/clocksource/timer-sp804.c @@ -24,12 +24,15 @@ #define HISI_TIMER_1_BASE 0x00 #define HISI_TIMER_2_BASE 0x40 #define HISI_TIMER_LOAD 0x00 +#define HISI_TIMER_LOAD_H 0x04 #define HISI_TIMER_VALUE 0x08 +#define HISI_TIMER_VALUE_H 0x0c #define HISI_TIMER_CTRL 0x10 #define HISI_TIMER_INTCLR 0x14 #define HISI_TIMER_RIS 0x18 #define HISI_TIMER_MIS 0x1c #define HISI_TIMER_BGLOAD 0x20 +#define HISI_TIMER_BGLOAD_H 0x24 struct sp804_timer __initdata arm_sp804_timer = { @@ -43,7 +46,9 @@ struct sp804_timer __initdata arm_sp804_timer = { struct sp804_timer __initdata hisi_sp804_timer = { .load = HISI_TIMER_LOAD, + .load_h = HISI_TIMER_LOAD_H, .value = HISI_TIMER_VALUE, + .value_h = HISI_TIMER_VALUE_H, .ctrl = HISI_TIMER_CTRL, .intclr = HISI_TIMER_INTCLR, .timer_base = {HISI_TIMER_1_BASE, HISI_TIMER_2_BASE}, @@ -129,6 +134,10 @@ int __init sp804_clocksource_and_sched_clock_init(void __iomem *base, writel(0, clkevt->ctrl); writel(0xffffffff, clkevt->load); writel(0xffffffff, clkevt->value); + if (clkevt->width == 64) { + writel(0xffffffff, clkevt->load_h); + writel(0xffffffff, clkevt->value_h); + } writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, clkevt->ctrl); @@ -245,7 +254,9 @@ static void __init sp804_clkevt_init(struct sp804_timer *timer, void __iomem *ba clkevt = &sp804_clkevt[i]; clkevt->base = timer_base; clkevt->load = timer_base + timer->load; + clkevt->load_h = timer_base + timer->load_h; clkevt->value = timer_base + timer->value; + clkevt->value_h = timer_base + timer->value_h; clkevt->ctrl = timer_base + timer->ctrl; clkevt->intclr = timer_base + timer->intclr; clkevt->width = timer->width;