From patchwork Fri Sep 18 13:22:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313193 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp1333540ilg; Fri, 18 Sep 2020 06:23:35 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz5r6KaZampNmrDn7FZVocleh+Bw5CBoZtgDSw7ncJfiLUeSak4oAHhlTfZumQvXfAbI+hx X-Received: by 2002:a17:906:d9d9:: with SMTP id qk25mr5497078ejb.51.1600435415054; Fri, 18 Sep 2020 06:23:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600435415; cv=none; d=google.com; s=arc-20160816; b=fxipUtflUHNo7qe+GRdEZoLspBKDK8guItZh9eJReh5WIh0Km47OYV2Q6Obf5b9FCM jCpE/ZhWxaXMMwpbju0ejNZN82cxqNhAAWApdbHRdk+g39EjTy8ffJx9CqZFabef31me JoFg/A7QV85bF+VZr+4uGIsZE8fkMsZEDQkPpVIcU5NPhTyU0sdNBLmKWFKNR3iE2PCW 2Tm1gMEflo5ia8FqQz3wJkjlofPjKRNchvPmxjuTWEPpAnFMnLz6IqfQ8xtNyKLtNgvs NGbRonJuSTKcKI48TfwoIxVO4+AC8RSy7GgIcgEYHWqU/upnno/2NNU7ZogoOP9moo38 P3cw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=Ak2K/FRL03EGVSH/tTthHxQGxbDG9z3BAcloOSqk2Nk=; b=ofdzobUrkWfWmp8Jjs3G8jLVW0z8yZZoDDAfY4EACSWT0WHHgiJEMFfCnws9Pwmite AbecfXJqLYXGnXmDZHT82oiPwohT5/8BLtQ24xOXFH3S70L9u+p2Y36jbyW6yvnVt6gK q5DnScmheCPOvfK7V+L8e/UwtJCY7fLTq6xVj8mrzmd0TqkCGnVBOdYXyMIFtRGh2aqk +3FbbZiwR/n1JgoY7rCyTZWISU9hTyOHu8atikXZrlGnVdvVoHbFC5GJtPW6zRMj1HN8 XL2UYQv2KtlbuxVJtWXJHrs2hiLVfTNMa28pKQoV5oDEfjVlZjvvgbv5/Fqh502XynaT Ztwg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id z1si2094545edx.584.2020.09.18.06.23.34; Fri, 18 Sep 2020 06:23:35 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726798AbgIRNXR (ORCPT + 6 others); Fri, 18 Sep 2020 09:23:17 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:59474 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726773AbgIRNXQ (ORCPT ); Fri, 18 Sep 2020 09:23:16 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 87433CAB032223C9E7FE; Fri, 18 Sep 2020 21:23:13 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Fri, 18 Sep 2020 21:23:02 +0800 From: Zhen Lei To: Rob Herring , devicetree , Daniel Lezcano , Thomas Gleixner , Haojian Zhuang , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang , Jianguo Chen Subject: [PATCH v3 7/9] clocksource: sp804: add support for Hisilicon sp804 timer Date: Fri, 18 Sep 2020 21:22:35 +0800 Message-ID: <20200918132237.3552-8-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200918132237.3552-1-thunder.leizhen@huawei.com> References: <20200918132237.3552-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The ARM SP804 supports a maximum of 32-bit counter, but Hisilicon extends it to 64-bit. That means, the registers: TimerXload, TimerXValue and TimerXBGLoad are 64bits, all other registers are the same as those in the SP804. The driver code can be completely reused except that the register offset is different. Use compatible = "hisilicon,sp804" mark as Hisilicon sp804 timer. Signed-off-by: Zhen Lei --- drivers/clocksource/timer-sp804.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) -- 1.8.3 diff --git a/drivers/clocksource/timer-sp804.c b/drivers/clocksource/timer-sp804.c index 5f4f979a8ef2c10..f0783d19522f048 100644 --- a/drivers/clocksource/timer-sp804.c +++ b/drivers/clocksource/timer-sp804.c @@ -20,6 +20,18 @@ #include "timer-sp.h" +/* Hisilicon 64-bit timer(a variant of ARM SP804) */ +#define HISI_TIMER_1_BASE 0x00 +#define HISI_TIMER_2_BASE 0x40 +#define HISI_TIMER_LOAD 0x00 +#define HISI_TIMER_VALUE 0x08 +#define HISI_TIMER_CTRL 0x10 +#define HISI_TIMER_INTCLR 0x14 +#define HISI_TIMER_RIS 0x18 +#define HISI_TIMER_MIS 0x1c +#define HISI_TIMER_BGLOAD 0x20 + + struct sp804_timer __initdata arm_sp804_timer = { .load = TIMER_LOAD, .value = TIMER_VALUE, @@ -29,6 +41,15 @@ struct sp804_timer __initdata arm_sp804_timer = { .width = 32, }; +struct sp804_timer __initdata hisi_sp804_timer = { + .load = HISI_TIMER_LOAD, + .value = HISI_TIMER_VALUE, + .ctrl = HISI_TIMER_CTRL, + .intclr = HISI_TIMER_INTCLR, + .timer_base = {HISI_TIMER_1_BASE, HISI_TIMER_2_BASE}, + .width = 64, +}; + static struct sp804_clkevt sp804_clkevt[NR_TIMERS]; static long __init sp804_get_clock_rate(struct clk *clk, const char *name) @@ -315,6 +336,12 @@ static int __init arm_sp804_of_init(struct device_node *np) } TIMER_OF_DECLARE(sp804, "arm,sp804", arm_sp804_of_init); +static int __init hisi_sp804_of_init(struct device_node *np) +{ + return sp804_of_init(np, &hisi_sp804_timer); +} +TIMER_OF_DECLARE(hisi_sp804, "hisilicon,sp804", hisi_sp804_of_init); + static int __init integrator_cp_of_init(struct device_node *np) { static int init_count = 0;