From patchwork Fri Sep 18 13:22:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313195 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp1333735ilg; Fri, 18 Sep 2020 06:23:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxdMiOALEuOEe8peKxX9LsKB4YC+iEP+raa9a7qwD7J4Zjrx9qAhvPoHXZpvMAEpag1BHz0 X-Received: by 2002:aa7:ce15:: with SMTP id d21mr38561953edv.284.1600435425900; Fri, 18 Sep 2020 06:23:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600435425; cv=none; d=google.com; s=arc-20160816; b=OYfcFhOPbDcnyhk7vj15I1EJX7HvuA2eG+OEz17vzFwZ1QAWvNqUs0j1D9y3Ilk8Mn W0FdaB+8F8e0r0SjWBvAonGtwdc3hbMZZNgDsKxY0WUCuxpJ5hMT8Ykc42UgzEaBjBIn 6Kr0bxWy764ijQUVJMpYP9LP4wY0kf9mDtA0C0QdaepJ3PeLy1rfXfxMJequ/FGnQyH/ MHVffWQVboo4Zt6jqUNcVnbR+n7vtc+umDxOBPcD3zgw4Xtai7rZF40zgqXL+QuqE9SK ICXNh9+bhQzKHfE9PyAwHeHnZADSd32xh8N2SjoRPVFTfGGxLSyMjUlscYgd1MTtSPCu FtbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=/Tmknmv4KzAmCc9Rf48zQegI5beZra8gPu4na4cvboM=; b=b6LpLKayK39qbhImgB13eRoet7hvO4XbeHlIDqG4teSCha/dYLg3WI4K286+mM+K78 aimnzzF/Pqq8HIyRzkAxb5qzpx2xcbjOs6A0v2lGiiTnAuNccexIFirHRKafEukCFM3B 19sxHyPMx+0WJ0OYfC1T+/a50RDCLIy6a0AgYHqla3xLT0CrkY4MPbeLQjBFjXDP12Pd 5M0BT7FkCRmYyopcNWwqImdC4Lgp2jfS/i/qKGkkniIcEjI3CTyta7ukIZeypE8bWUID grs2KxpZubbX4QS7uYdLTl+gxhdJxzeuDopiy8LdnX1BWZof2deMf81uryikFel+Ty9j YJcA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id v5si2186445edr.49.2020.09.18.06.23.45; Fri, 18 Sep 2020 06:23:45 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726846AbgIRNXf (ORCPT + 6 others); Fri, 18 Sep 2020 09:23:35 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:13309 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726698AbgIRNXN (ORCPT ); Fri, 18 Sep 2020 09:23:13 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 89F52A4931A7FB1009A9; Fri, 18 Sep 2020 21:23:08 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Fri, 18 Sep 2020 21:23:02 +0800 From: Zhen Lei To: Rob Herring , devicetree , Daniel Lezcano , Thomas Gleixner , Haojian Zhuang , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang , Jianguo Chen Subject: [PATCH v3 6/9] clocksource: sp804: support non-standard register offset Date: Fri, 18 Sep 2020 21:22:34 +0800 Message-ID: <20200918132237.3552-7-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200918132237.3552-1-thunder.leizhen@huawei.com> References: <20200918132237.3552-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The ARM SP804 supports a maximum of 32-bit counter, but Hisilicon extends it to 64-bit. That means, the registers: TimerXload, TimerXValue and TimerXBGLoad are 64bits, all other registers are the same as those in the SP804. The driver code can be completely reused except that the register offset is different. Currently, we get a timer register address by: add the constant register offset to the timer base address. e.g. "base + TIMER_CTRL". It can not be dynamically adjusted at run time. So create a new structure "sp804_timer" to record the original registers offset, and create a new structure "sp804_clkevt" to record the calculated registers address. So the "base + TIMER_CTRL" is changed to "clkevt->ctrl", this will faster than "base + timer->ctrl". For example: struct sp804_timer arm_sp804_timer = { .ctrl = TIMER_CTRL, }; struct sp804_clkevt clkevt; clkevt.ctrl = base + arm_sp804_timer.ctrl. - writel(0, base + TIMER_CTRL); + writel(0, clkevt->ctrl); Signed-off-by: Zhen Lei --- drivers/clocksource/timer-sp.h | 26 +++++++++ drivers/clocksource/timer-sp804.c | 108 +++++++++++++++++++++++++++++--------- 2 files changed, 108 insertions(+), 26 deletions(-) -- 1.8.3 diff --git a/drivers/clocksource/timer-sp.h b/drivers/clocksource/timer-sp.h index b2037eb94a41485..1ab75cbed0e09e5 100644 --- a/drivers/clocksource/timer-sp.h +++ b/drivers/clocksource/timer-sp.h @@ -10,6 +10,7 @@ * * Every SP804 contains two identical timers. */ +#define NR_TIMERS 2 #define TIMER_1_BASE 0x00 #define TIMER_2_BASE 0x20 @@ -29,3 +30,28 @@ #define TIMER_RIS 0x10 /* CVR ro */ #define TIMER_MIS 0x14 /* CVR ro */ #define TIMER_BGLOAD 0x18 /* CVR rw */ + +struct sp804_timer { + int load; + int value; + int ctrl; + int intclr; + int ris; + int mis; + int bgload; + int timer_base[NR_TIMERS]; + int width; +}; + +struct sp804_clkevt { + void __iomem *base; + void __iomem *load; + void __iomem *value; + void __iomem *ctrl; + void __iomem *intclr; + void __iomem *ris; + void __iomem *mis; + void __iomem *bgload; + unsigned long reload; + int width; +}; diff --git a/drivers/clocksource/timer-sp804.c b/drivers/clocksource/timer-sp804.c index 471c5c6aaf51afd..5f4f979a8ef2c10 100644 --- a/drivers/clocksource/timer-sp804.c +++ b/drivers/clocksource/timer-sp804.c @@ -20,6 +20,17 @@ #include "timer-sp.h" +struct sp804_timer __initdata arm_sp804_timer = { + .load = TIMER_LOAD, + .value = TIMER_VALUE, + .ctrl = TIMER_CTRL, + .intclr = TIMER_INTCLR, + .timer_base = {TIMER_1_BASE, TIMER_2_BASE}, + .width = 32, +}; + +static struct sp804_clkevt sp804_clkevt[NR_TIMERS]; + static long __init sp804_get_clock_rate(struct clk *clk, const char *name) { long rate; @@ -58,11 +69,26 @@ static long __init sp804_get_clock_rate(struct clk *clk, const char *name) return rate; } -static void __iomem *sched_clock_base; +static struct sp804_clkevt * __init sp804_clkevt_get(void __iomem *base) +{ + int i; + + for (i = 0; i < NR_TIMERS; i++) { + if (sp804_clkevt[i].base == base) + return &sp804_clkevt[i]; + } + + /* It's impossible to reach here */ + WARN_ON(1); + + return NULL; +} + +static struct sp804_clkevt *sched_clkevt; static u64 notrace sp804_read(void) { - return ~readl_relaxed(sched_clock_base + TIMER_VALUE); + return ~readl_relaxed(sched_clkevt->value); } int __init sp804_clocksource_and_sched_clock_init(void __iomem *base, @@ -71,22 +97,25 @@ int __init sp804_clocksource_and_sched_clock_init(void __iomem *base, int use_sched_clock) { long rate; + struct sp804_clkevt *clkevt; rate = sp804_get_clock_rate(clk, name); if (rate < 0) return -EINVAL; - writel(0, base + TIMER_CTRL); - writel(0xffffffff, base + TIMER_LOAD); - writel(0xffffffff, base + TIMER_VALUE); + clkevt = sp804_clkevt_get(base); + + writel(0, clkevt->ctrl); + writel(0xffffffff, clkevt->load); + writel(0xffffffff, clkevt->value); writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, - base + TIMER_CTRL); + clkevt->ctrl); - clocksource_mmio_init(base + TIMER_VALUE, name, + clocksource_mmio_init(clkevt->value, name, rate, 200, 32, clocksource_mmio_readl_down); if (use_sched_clock) { - sched_clock_base = base; + sched_clkevt = clkevt; sched_clock_register(sp804_read, 32, rate); } @@ -94,8 +123,7 @@ int __init sp804_clocksource_and_sched_clock_init(void __iomem *base, } -static void __iomem *clkevt_base; -static unsigned long clkevt_reload; +static struct sp804_clkevt *common_clkevt; /* * IRQ handler for the timer @@ -105,7 +133,7 @@ static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id) struct clock_event_device *evt = dev_id; /* clear the interrupt */ - writel(1, clkevt_base + TIMER_INTCLR); + writel(1, common_clkevt->intclr); evt->event_handler(evt); @@ -114,7 +142,7 @@ static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id) static inline void timer_shutdown(struct clock_event_device *evt) { - writel(0, clkevt_base + TIMER_CTRL); + writel(0, common_clkevt->ctrl); } static int sp804_shutdown(struct clock_event_device *evt) @@ -129,8 +157,8 @@ static int sp804_set_periodic(struct clock_event_device *evt) TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE; timer_shutdown(evt); - writel(clkevt_reload, clkevt_base + TIMER_LOAD); - writel(ctrl, clkevt_base + TIMER_CTRL); + writel(common_clkevt->reload, common_clkevt->load); + writel(ctrl, common_clkevt->ctrl); return 0; } @@ -140,8 +168,8 @@ static int sp804_set_next_event(unsigned long next, unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ONESHOT | TIMER_CTRL_ENABLE; - writel(next, clkevt_base + TIMER_LOAD); - writel(ctrl, clkevt_base + TIMER_CTRL); + writel(next, common_clkevt->load); + writel(ctrl, common_clkevt->ctrl); return 0; } @@ -168,13 +196,13 @@ int __init sp804_clockevents_init(void __iomem *base, unsigned int irq, if (rate < 0) return -EINVAL; - clkevt_base = base; - clkevt_reload = DIV_ROUND_CLOSEST(rate, HZ); + common_clkevt = sp804_clkevt_get(base); + common_clkevt->reload = DIV_ROUND_CLOSEST(rate, HZ); evt->name = name; evt->irq = irq; evt->cpumask = cpu_possible_mask; - writel(0, base + TIMER_CTRL); + writel(0, common_clkevt->ctrl); if (request_irq(irq, sp804_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL, "timer", &sp804_clockevent)) @@ -184,7 +212,26 @@ int __init sp804_clockevents_init(void __iomem *base, unsigned int irq, return 0; } -static int __init sp804_of_init(struct device_node *np) +static void __init sp804_clkevt_init(struct sp804_timer *timer, void __iomem *base) +{ + int i; + + for (i = 0; i < NR_TIMERS; i++) { + void __iomem *timer_base; + struct sp804_clkevt *clkevt; + + timer_base = base + timer->timer_base[i]; + clkevt = &sp804_clkevt[i]; + clkevt->base = timer_base; + clkevt->load = timer_base + timer->load; + clkevt->value = timer_base + timer->value; + clkevt->ctrl = timer_base + timer->ctrl; + clkevt->intclr = timer_base + timer->intclr; + clkevt->width = timer->width; + } +} + +static int __init sp804_of_init(struct device_node *np, struct sp804_timer *timer) { static bool initialized = false; void __iomem *base; @@ -199,12 +246,12 @@ static int __init sp804_of_init(struct device_node *np) if (!base) return -ENXIO; - timer1_base = base; - timer2_base = base + TIMER_2_BASE; + timer1_base = base + timer->timer_base[0]; + timer2_base = base + timer->timer_base[1]; /* Ensure timers are disabled */ - writel(0, timer1_base + TIMER_CTRL); - writel(0, timer2_base + TIMER_CTRL); + writel(0, timer1_base + timer->ctrl); + writel(0, timer2_base + timer->ctrl); if (initialized || !of_device_is_available(np)) { ret = -EINVAL; @@ -230,6 +277,8 @@ static int __init sp804_of_init(struct device_node *np) if (irq <= 0) goto err; + sp804_clkevt_init(timer, base); + of_property_read_u32(np, "arm,sp804-has-irq", &irq_num); if (irq_num == 2) { @@ -259,7 +308,12 @@ static int __init sp804_of_init(struct device_node *np) iounmap(base); return ret; } -TIMER_OF_DECLARE(sp804, "arm,sp804", sp804_of_init); + +static int __init arm_sp804_of_init(struct device_node *np) +{ + return sp804_of_init(np, &arm_sp804_timer); +} +TIMER_OF_DECLARE(sp804, "arm,sp804", arm_sp804_of_init); static int __init integrator_cp_of_init(struct device_node *np) { @@ -282,11 +336,13 @@ static int __init integrator_cp_of_init(struct device_node *np) } /* Ensure timer is disabled */ - writel(0, base + TIMER_CTRL); + writel(0, base + arm_sp804_timer.ctrl); if (init_count == 2 || !of_device_is_available(np)) goto err; + sp804_clkevt_init(&arm_sp804_timer, base); + if (!init_count) { ret = sp804_clocksource_and_sched_clock_init(base, name, clk, 0);