From patchwork Fri Sep 18 13:22:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313196 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp1333751ilg; Fri, 18 Sep 2020 06:23:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyiN3TivbsGCFsZb0LKIFRddY3e75X9+v9DDAwRezutRStnlrtK1XITr1AXHI0jFvifr2Ab X-Received: by 2002:a17:906:1e51:: with SMTP id i17mr37295643ejj.103.1600435426925; Fri, 18 Sep 2020 06:23:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600435426; cv=none; d=google.com; s=arc-20160816; b=vQMXIrRrQK4QMwnItxXb6ofV6b3XAZUon8eHEBK2x+JeaoMPwN6/n4nLdrCo+sVXCF +krcr6uuRvsASAbUw5pE34XwLW0Hwb8k71sDr/Hz9OAURLjPwLslWwFsN/nYoDmdyEBI Td+wfk4pIUr/H/DZLh3IMqsSCxhQBj4HN4CFoKvR9Stvo2Ip13lpmhLBqu4gXs4DKIBb /iFznBO5HgVbpjbBJiR8+XrTgeYihAPR9sxPoPIIjBuYeelvOSzoQaAOTTs0QIEJTx3F OjXxoIgZZEv73tKIzkxbxyyWVsnDdkZb/p/vPvDg4e53FcBaEt6HRJYFTDA3BwRmpCZ4 Z7sw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=hMZZAXeX7ChwqJ4QB1x1fLjSU0j10qLtJPtwbE00CZ0=; b=RSrlSYi3fR4hXi505RpTdUjyz4Fr7aR5RSNY7KpJ0+BslEHymO9QAMMGtsXriJfBzV 9pfHVGEJpiERmMLBteqcPnYUVLcHMipqQNrRLRNdrfv3jDH0EpPbOJVyaHdoBg6SgICM o2p0lJJb7+96WH1KhEeklU/EAzpb+uIWjRFo3dXVUFmYQZZ3VCuLMJPOPf5EXacrqohG k9ZE8XTUR8rTTgfJlqgh5m5YJ5A+9nvcVXQzjJSoKZvXdSrqbE6WRaEIZyyoVZ/Si3Z3 VOekZPYIgjsDDD8KbVADloe2JorFc1Xob8/MK7n7AHVKY+1II/SDY70aA2o6oa524Q7l vXoQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id v5si2186445edr.49.2020.09.18.06.23.46; Fri, 18 Sep 2020 06:23:46 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726126AbgIRNXp (ORCPT + 6 others); Fri, 18 Sep 2020 09:23:45 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:13304 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726239AbgIRNXM (ORCPT ); Fri, 18 Sep 2020 09:23:12 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 854B552CD0D633A645F3; Fri, 18 Sep 2020 21:23:08 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Fri, 18 Sep 2020 21:23:01 +0800 From: Zhen Lei To: Rob Herring , devicetree , Daniel Lezcano , Thomas Gleixner , Haojian Zhuang , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang , Jianguo Chen Subject: [PATCH v3 5/9] clocksource: sp804: prepare for support non-standard register offset Date: Fri, 18 Sep 2020 21:22:33 +0800 Message-ID: <20200918132237.3552-6-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200918132237.3552-1-thunder.leizhen@huawei.com> References: <20200918132237.3552-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add two local variables: timer1_base and timer2_base in sp804_of_init(), to avoid repeatedly calculate the base address of timer2, and make it easier to recognize timer1. Hope to make the next patch looks more clear. No functional change. Signed-off-by: Zhen Lei --- drivers/clocksource/timer-sp804.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) -- 1.8.3 diff --git a/drivers/clocksource/timer-sp804.c b/drivers/clocksource/timer-sp804.c index a443f392a8e7d63..471c5c6aaf51afd 100644 --- a/drivers/clocksource/timer-sp804.c +++ b/drivers/clocksource/timer-sp804.c @@ -188,6 +188,8 @@ static int __init sp804_of_init(struct device_node *np) { static bool initialized = false; void __iomem *base; + void __iomem *timer1_base; + void __iomem *timer2_base; int irq, ret = -EINVAL; u32 irq_num = 0; struct clk *clk1, *clk2; @@ -197,9 +199,12 @@ static int __init sp804_of_init(struct device_node *np) if (!base) return -ENXIO; + timer1_base = base; + timer2_base = base + TIMER_2_BASE; + /* Ensure timers are disabled */ - writel(0, base + TIMER_CTRL); - writel(0, base + TIMER_2_BASE + TIMER_CTRL); + writel(0, timer1_base + TIMER_CTRL); + writel(0, timer2_base + TIMER_CTRL); if (initialized || !of_device_is_available(np)) { ret = -EINVAL; @@ -228,21 +233,21 @@ static int __init sp804_of_init(struct device_node *np) of_property_read_u32(np, "arm,sp804-has-irq", &irq_num); if (irq_num == 2) { - ret = sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name); + ret = sp804_clockevents_init(timer2_base, irq, clk2, name); if (ret) goto err; - ret = sp804_clocksource_and_sched_clock_init(base, + ret = sp804_clocksource_and_sched_clock_init(timer1_base, name, clk1, 1); if (ret) goto err; } else { - ret = sp804_clockevents_init(base, irq, clk1, name); + ret = sp804_clockevents_init(timer1_base, irq, clk1, name); if (ret) goto err; - ret = sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE, + ret = sp804_clocksource_and_sched_clock_init(timer2_base, name, clk2, 1); if (ret) goto err;