From patchwork Mon Sep 14 15:21:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 303458 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp1724188ilg; Mon, 14 Sep 2020 08:21:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwkx9di9o673RVrA4AwEAr5zmBzoR9a5D5Fl8nP9nWxYGylGANhss35qAZqXvUJDRumXb6m X-Received: by 2002:a05:6402:503:: with SMTP id m3mr17994776edv.45.1600096915548; Mon, 14 Sep 2020 08:21:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600096915; cv=none; d=google.com; s=arc-20160816; b=tqq5xPv/rYxygqjkPddZnz3LQWriD5Yy431pdYVLfZP17+RpBdorX869kzkhjXrYiG 9awYGOQ/9CCkjykU7834ODh7O93D/8n5ahtnJmmsyT6Rx6iatS7+fpeKojDEo+htfgXO EwJKda+bmgt4ejkwhy7QvXwiQDcTfzQIko0/q9e48bCHa5Fi12FJ/6RwN2YO2ecYo8Jf XH5Hn89qncBj9j7yZQN81Cy19Ued1w0JKJJV6TE48sc1lCpjOv88Blbd2bcM+ERnsZNs QVq2yQCAm0iSJ7NhPX6jRVvrHCKQPSVlPXnwCiBsnf2iif+dQ0Mq2zcujYN2txI/f/RN vswQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=RixAWEvCOs5TI6IoAywsdosmAxAkvKzfEAycZgP8sUM=; b=S96lG2ySIdN5aMR7n2lSDnBnCZ4+hhWSpFn6FENMvn21SC8k2gSRXtBtObCDDpSwcp QBhJX2FnZ/l7hw9pUT3piFrOb9ys64ZBvMnxurq19Bsa6thGVJi/B5DovzCSc6OKRdxG 776i+Xgr39sGPOtoLOc4tmViKwrcO/lzr6jVTnj+umM1e+3rvq4s8VGglACQPnh0dlIh f/0suvH3Y44Idg8k0Orx/ZdL/lTCs56kF8rnP4fIRqWS1T1GRYdpUkPgbPpOxR0CzD+I wmqAlVmRzETV3Ktz44cJY7HNekMx59bSAINBBCrK8t71mP2Yh6rAqCOLHg5TEhQL+AhG gZ0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=HzECdmfC; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id d23si7590262edt.338.2020.09.14.08.21.55; Mon, 14 Sep 2020 08:21:55 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=HzECdmfC; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726477AbgINPVw (ORCPT + 6 others); Mon, 14 Sep 2020 11:21:52 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:59512 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726471AbgINPVo (ORCPT ); Mon, 14 Sep 2020 11:21:44 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 08EFLWeW056092; Mon, 14 Sep 2020 10:21:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1600096892; bh=RixAWEvCOs5TI6IoAywsdosmAxAkvKzfEAycZgP8sUM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=HzECdmfChsgYF/+kfO9MD4zsaE2DMZMqdRvTrv5DXFtdYjJsnJA7ZXzScXBciKJA1 ACAS00dA2TuYK+cw3vz8l9SUV9ayMO2N5wLZCUwhHsXTirUWVtj6UXD5nKC0D3NYuZ xvAHXDBTnF6xej1iUwNEkoNbTOAN/3uspw/bsFb4= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 08EFLWrX062433 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Sep 2020 10:21:32 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 14 Sep 2020 10:21:32 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 14 Sep 2020 10:21:32 -0500 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 08EFLNOR103257; Mon, 14 Sep 2020 10:21:30 -0500 From: Kishon Vijay Abraham I To: Tero Kristo , Nishanth Menon , Rob Herring CC: , , , Kishon Vijay Abraham I Subject: [PATCH v2 2/2] arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances Date: Mon, 14 Sep 2020 20:51:15 +0530 Message-ID: <20200914152115.1788-3-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200914152115.1788-1-kishon@ti.com> References: <20200914152115.1788-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org J721E Common Processor Board has PCIe connectors for the 1st three PCIe instances. Configure the three PCIe instances in RC mode and disable the 4th PCIe instance. Signed-off-by: Kishon Vijay Abraham I --- .../dts/ti/k3-j721e-common-proc-board.dts | 80 +++++++++++++++++++ 1 file changed, 80 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index c355692796a9..8b57d22ca3cc 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -558,3 +558,83 @@ status = "okay"; }; + +&serdes0 { + serdes0_pcie_link: link@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>; + }; +}; + +&serdes1 { + serdes1_pcie_link: link@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; + }; +}; + +&serdes2 { + serdes2_pcie_link: link@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>; + }; +}; + +&pcie0_rc { + reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; +}; + +&pcie1_rc { + reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; + phys = <&serdes1_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; +}; + +&pcie2_rc { + reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>; + phys = <&serdes2_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; +}; + +&pcie0_ep { + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; + status = "disabled"; +}; + +&pcie1_ep { + phys = <&serdes1_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; + status = "disabled"; +}; + +&pcie2_ep { + phys = <&serdes2_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; + status = "disabled"; +}; + +&pcie3_rc { + status = "disabled"; +}; + +&pcie3_ep { + status = "disabled"; +};